11274-001 AMI Semiconductor, Inc., 11274-001 Datasheet - Page 38

• Manufacturer Part Number: 11274-001
• Description: Logic and Timing, Programmable Line Lock Clock Generator IC, Tape and Reel
• Manufacturer: AMI Semiconductor, Inc.

FS6131-01
FS6131-01
FS6131-01
FS6131-01
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
15.0
The FS6131 can be used as a clock regenerator as
shown in Figure 33. This mode uses the voltage-
controlled crystal oscillator (VCXO) in its own phase-
locked loop, referred to as the Crystal Loop. The VCXO
provides a "de-jittered" multiple of the reference fre-
quency at the REF pin (usually 8kHz in telecom applica-
tions) for use by the Main Loop. In essence, the Crystal
Loop “cleans up” the reference signal for the Main Loop.
The Control ROM for the VCXO Divider is preloaded with
the most common ratios to permit locking of most stan-
dard telecommunications crystals to an 8kHz signal ap-
plied to the REF pin. The de-jittered multiple of the refer-
ence frequency from the VCXO is then supplied to the
Reference Divider in the Main Loop. The Reference Di-
vider, along with the Feedback Divider, can be pro-
grammed to achieve the desired output clock frequency.
Figure 33: Block Diagram: Telecom Clock Regenerator
(typical)
8kHz IN
(optional)
XOUT
SDA
REF
FBK
SCL
XTUNE
(optional)
XIN
ADDR
Device Application:
Telecom Clock Regenerator
REFDSRC
Interface
(f
REF
VCXO
I
2
)
C
XCT[3:0],
XLVTEN
Reference
REFDIV[11:0]
Divider
(N
R
)
Registers
Control
Divider
VCXO
ROM
PDREF
PDFBK
Frequency
XLROM[2:0]
Detector
Phase-
Frequency
Detector
Phase-
XLPDEN,
XLSWAP
Divider
Feedback
FBKDIV[14:0]
DOWN
UP
(N
CRYSTAL LOOP
Charge
MLCP[1:0]
Pump
F
)
DOWN
UP
38
Charge
XLCP[1:0]
Pump
FBKDSRC[1:0]
15.1
A Visual BASIC program is available to completely pro-
gram the FS6131 based on the given parameters.
In this example, an 8kHz reference frequency is supplied
to the FS6131 and an output clock frequency of
51.84MHz is desired.
First, select the frequency at which the VCXO will operate
from Table 10. The table shows the external crystal fre-
quency options available to choose from, since the VCXO
runs at the crystal frequency. While the Main Loop can be
programmed to work with any of the frequencies in the
table, the best performance will be achieved with the
highest frequency at the Main Loop PFD.
The frequency at the Main Loop PFD (f
frequency (f
Divider (N
Controlled
Oscillator
Voltage
OSCTYPE
VCOSPD,
Example Calculation
R
).
VCXO
(f
VCO
OM[1:0]
)
) divided by the Main Loop Reference
MAIN LOOP
Gobbler
EXTLF
Clock
GBL
Internal
Loop
Filter
LFTC
f
MLpfd
POST3[1:0],
POST2[1:0],
POST1[1:0]
Divider
(N
Post
Px
f
)
N
VCXO
Detect
STAT[1:0]
FS6131
R
Lock
CMOS/PECL
Output
MLpfd
CMOS
) is the VCXO
C
R
LF
LF
C
EXTLF
(optional)
LOCK/
IPRG
(optional)
CLKP
CLKN
LP
R
IPRG
(f
CLK
)