11274-001 AMI Semiconductor, Inc., 11274-001 Datasheet - Page 35

• Manufacturer Part Number: 11274-001
• Description: Logic and Timing, Programmable Line Lock Clock Generator IC, Tape and Reel
• Manufacturer: AMI Semiconductor, Inc.

However, the 31.5kHz line reference signal is too low in
frequency for the internal loop filter to be used. A series
combination of a 0.015 F capacitor and a 15k
from power (V
loop filter. A 100pF to 220pF capacitor in parallel with the
combination may improve the filter performance.
For the best PLL performance, program the Post Divider
modulus to allow the VCO to operate at a nominal fre-
quency that is at least 70MHz but less then 230MHz. The
VCO frequency (f
Setting the Post Divider equal to four (N
sonable solution, although there are a number of values
that will work. Try to keep
to avoid divider values from becoming too large. These
settings place the VCO frequency at about 100MHz.
Calculate the ideal charge pump current (I
where R
the external loop filter series capacitor, and A
VCO gain. The VCO gain is either:
See Table 16 for more information on the VCO range.
With f
N
39.3 A. A 220pF cap across the entire loop filter is also
helpful.
Px
=4, and A
hsync
A
A
lf
VCO
VCO
is the external loop filter series resistor, C
=31.5kHz, C
=125MHz/V if the High Range is selected, or
=75MHz/V if the Low Range is selected.
VCO
I
DD
pump
f
=125MHz/V, the charge pump current is
) to the EXTLF pin provides an external
VCO
VCO
) can be calculated by
N
F
15
f
f
HSYNC
HSYNC
lf
=0.015 F, R
kHz
N
Px
N
5000
R
F
2
lf
2
N
C
F
lf
N
N
A
lf
Px
=15k , N
VCO
Px
.
pump
Px
=4) is a rea-
) as
VCO
resistor
F
is the
=800,
lf
is
35
13.2
To generate 800 pixel clocks between HSYNC pulses
occurring on the line reference signal every 31.5kHz,
program the following (refer to Figure 31):
The output clock frequency f
internal VCO frequency of 100.8MHz. Note that the
Crystal Loop was unused in this application.
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Clear the OSCTYPE bit to 0
Turn off the crystal oscillator via XLROM=7
Set the PFD inputs to select the REF pin and the
Feedback Divider via PDREF=1 and PDFBK=0
Set the Feedback Divider input to select the Post Di-
vider via FBKDSRC=0
Set the Feedback Divider (N
(the desired number of pixel clocks per line) via
FBKDIV[14:0]
Set N
Divider modulus of N
POST2[1:0], and POST3[1:0].
Select the external loop filter via EXTLF=1
Set XLVTEN=0 and XLPDEN=1 to disable the VCXO
fine tune and the Crystal Loop Phase Frequency
Detector
Set VCOSPD=1 to select the VCO low speed range
Set MLCP[1:0] to 3 to select the 32 A range
Example Programming
P1
=4, N
P2
=1, and N
Px
=4 via POST1[1:0],
P3
CLK
=1 for a combined Post
FS6131-01
FS6131-01
FS6131-01
FS6131-01
F
) to a modulus of 800
is 25.175MHz, with an