11274-001 AMI Semiconductor, Inc., 11274-001 Datasheet - Page 37

• Manufacturer Part Number: 11274-001
• Description: Logic and Timing, Programmable Line Lock Clock Generator IC, Tape and Reel
• Manufacturer: AMI Semiconductor, Inc.

The output clock frequency is calculated as
For best performance, program the Post Divider (N
modulus to allow the VCO to operate at a nominal fre-
quency that is at least 70MHz but less then 230MHz. The
VCO frequency (f
Selecting the Post Divider modulus of N
able solution, although there are a number of values that
will work. Try to keep
to avoid divider values from becoming too large. The set-
tings place the VCO frequency at about 72MHz.
Calculate the ideal charge pump current (I
where R
the external loop filter series capacitor, and A
VCO gain. The VCO gain is either
See Table 16 for more information on the VCO range.
With f
and A
A 220pF cap across the entire loop filter is also helpful.
hsync
VCO
A
A
lf
=125MHz/V, the charge pump current is 24 A.
VCO
VCO
=15kHz, C
is the external loop filter series resistor, C
f
=125MHz/V if the High Range is selected, or
=75MHz/V if the Low Range is selected.
CLK
I
pump
VCO
15
lf
) can be calculated by
N
=0.015 F, R
f
kHz
VCO
F
15
f
HSYNC
kHz
N
Px
f
800
CLK
5000
N
R
lf
2
lf
=15k , N
2
Px
12
N
C
.
F
lf
0 .
N
A
MHz
VCO
Px
Px
pump
=6 is a reason-
F
=800, N
) as
.
VCO
is the
Px
lf
=6,
Px
is
)
37
14.2
To generate 800 pixel clocks between HSYNC pulses
occurring on the line reference signal every 15kHz, pro-
gram the following (refer to Figure 32):
The output clock frequency f
VCO frequency of 72MHz. Note that the Crystal Loop
was unused in this application.
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Clear the OSCTYPE bit to 0
Turn off the crystal oscillator via XLROM=7
Set the PFD inputs to select the REF and FBK pins
via PDREF=1 and PDFBK=1
Set N
Divider modulus of N
POST2[1:0], and POST3[1:0].
Select the external loop filter via EXTLF=1
Set XLVTEN=0 and XLPDEN=1 to disable the VCXO
fine tune and the Crystal Loop Phase Frequency
Detector
Set VCOSPD=1 to select the VCO low speed range
Set MLCP[1:0] to 3 to select the 32 A range
Example Programming
P1
=2, N
P2
=3, and N
Px
=6 via POST1[1:0],
CLK
P3
=1 for a combined Post
FS6131-01
FS6131-01
is 12MHz, with an internal
FS6131-01
FS6131-01