11274-001 AMI Semiconductor, Inc., 11274-001 Datasheet - Page 33

• Manufacturer Part Number: 11274-001
• Description: Logic and Timing, Programmable Line Lock Clock Generator IC, Tape and Reel
• Manufacturer: AMI Semiconductor, Inc.

Next, express the output and input frequencies as a ratio
of f
product of prime numbers.
Simplifying the above equation yields
Deciding how to apportion the denominator integers be-
tween the Reference Divider and the Post Divider is an
iterative process. To obtain the best performance, the
VCO should be operated at the highest frequency possi-
ble without exceeding its upper limit of 230MHz. (see
Table 16). The VCO frequency (f
by
Recall that the Reference Divider can have a value be-
tween 1 and 4096, but the Post Divider is limited to val-
ues derived from
where the values N
In this example, the smallest integer that can be removed
from the denominator of Eqn. 2 is three. Set the Post Di-
vider at N
Eqn. 1)
Unfortunately, a Post Divider modulus of three requires a
VCO frequency of 300MHz, which is greater than the al-
lowable f
formance, program the Post Divider modulus to allow the
VCO to operate at a nominal frequency that is at least
70MHz but less then 230MHz. Therefore, the Reference
Divider cannot be reduced below the modulus of 3
63) as shown in Eqn. 2.
However, the VCO can still be operated at a frequency
higher than f
denominator by two does not alter the output frequency,
but it does increase the VCO frequency.
CLK
f
f
CLK
REF
to f
VCO
Px
f
f
CLK
REF
REF
=3, and the ratio of f
N
N
CLK
f
f
, where f
noted in Table 16. For the best PLL per-
F
R
CLK
REF
. Multiplying both the numerator and the
100000000
14318181
N
f
f
N
CLK
REF
1
P1
Px
Px
f
2
VCO
, N
3
CLK
3
P2
N
2
(Eqn. 3)
2
5
2
, and N
P
.
3
1
.
81
3
has also been converted to a
1
f
00
7
REF
3
3
11
5
5
N
2
1
1
7
P
CLK
æ
ç ç
è
.
2
P3
11
11
7
2
N
N
VCO
5
are found in Table 8.
to f
F
R
N
2
(Eqn. 2)
3
) can be calculated
.
2
P
1
8
3
2
11
REF
3
.
5
5
1
2
7
becomes (from
8
7
880
63
1
ö
÷ ÷
ø
2
1
2
7 (or
33
As Eqn. 3 shows, the VCO frequency can be doubled by
multiplying the Feedback Divider by two. Set the Post
Divider to two to return the output frequency to the de-
sired modulus. These divider settings place the VCO fre-
quency at 200MHz.
12.2
To generate 100.000MHz from 14.318MHz, program the
following (refer to Figure 30):
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Set the Reference Divider input to select the VCXO
via REFDSRC=0
Set the PFD input to select the Reference Divider
and the Feedback Divider via PDREF=0 and
PDFBK=0
Set the Reference Divider (N
REFDIV[11:0]
Set the Feedback Divider input to select the VCO via
FBKDSRC=1
Set the Feedback Divider (N
via FBKDIV[14:0]
Set N
Divider modulus of N
POST2[1:0], and POST3[1:0].
Select the internal loop filter via EXTLF=0
Set XLVTEN=0 and XLPDEN=1 to disable the VCXO
fine tune and the Crystal Loop Phase Frequency
Detector
Set VCOSPD=0 to select the VCO high speed range
Example Programming
P1
=2, N
P2
=1, and N
Px
=2 via POST1[1:0],
P3
=1 for a combined Post
FS6131-01
FS6131-01
FS6131-01
FS6131-01
F
R
) to a modulus of 880
) to a modulus of 63 via