STG3005A2S STMicroelectronics, STG3005A2S Datasheet - Page 21

• Manufacturer Part Number: STG3005A2S
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

128-BIT 3D MULTIMEDIA ACCELERATOR
AGP timing specification
Figure 12. AGP clock specification
Table 1. AGP clock timing parameters
NOTES
Figure 13. AGP timing diagram
Table 2. AGP timing parameters
Symbol
t
t
t
t
t
PCICLK
Symbol
t
t
t
VAL
ON
OFF
SU
H
CYC
HIGH
LOW
1 This rise and fall time is measured across the minimum peak-to-peak range as shown in Figure 12.
Tri-state output
0.5VDD
0.4VDD
0.3VDD
AGPCLK to signal valid delay (data and control
signals)
Float to active delay
Active to float delay
Input set up time to AGPCLK (data and control
signals)
Input hold time from AGPCLK
PCICLK period
PCICLK high time
PCICLK low time
PCICLK slew rate
Output delay
AGPCLK
Input
0.6VDD
Parameter
Parameter
t
CYC
t
ON
t
VAL
0.2VDD
t
OFF
data1
t
SU
data1
Min.
Min.
1.5
15
2
2
7
0
6
6
t
HIGH
t
H
t
VAL
Max.
Max.
11
28
30
4
data2
t
data2
LOW
Unit
Unit
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
RIVA128ZX
(minimum)
Notes
Notes
2V p-to-p
1
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