STG3005A2S STMicroelectronics, STG3005A2S Datasheet - Page 45

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STG3005A2S

Manufacturer Part Number
STG3005A2S
Description
128-BIT 3D MULTIMEDIA ACCELERATOR
Manufacturer
STMicroelectronics
Datasheet
128-BIT 3D MULTIMEDIA ACCELERATOR
8
The RIVA128ZX Multimedia Accelerator introduc-
es a multi-function Video Port that has been de-
signed to exploit the bus mastering functionality of
the RIVA128ZX. The Video Port is compliant with
a simplified ITU-R-656 video format with control of
attached video devices performed through the
RIVA128ZX serial interface. Video Port support in-
cludes:
Figure 45. Connections to multiple video modules
8.1
Windows 95 DirectMPEG API acceleration by
providing:
- Bus mastered compressed data transfer to
Single 8-bit bus multiplexing among four trans-
fer types: video, VBI, host and compressed
data
Synchronous 40MHz address/data multiplexed
bus
Hardware-based round-robin scheduler with
predictable performance for all transfer types
PCI/AGP
VIDEO PORT
attached DVD and MPEG-2 decoders
VIDEO INTERFACE PORT FEATURES
RIVA128ZX
SDA
SCL
MPCLK
MPAD[7:0]
MPFRAME#
MPDTACK#
MPSTOP#
- Local interrupt and pixel stream handling
- Hardware buffer management of com-
Supports popular video decoders including the
Philips SAA7111A, SAA7112, ITT 3225, and
Samsung KS0127. The Video Port initiates
transfers of video packets over the internal NV
bus to either on or off screen surfaces as de-
fined in the DirectDraw and DirectVideo APIs.
Supports filtered down-scaling or decimation
Allows additional devices to be added
Supports multiple video modules and one rib-
bon cable board on the same bus
ITU-R-656 Master Mode
Video Port
- Simplified ITU-R-656 Video Format -- sup-
- VBI data output from video decoder is cap-
Media Port
pressed data, decompressed video pixel
data and decompressed audio streams
ports HSYNC, VSYNC, ODD FIELD and
EVEN FIELD
tured as raw or sliced data
Controller
decoder
(MPC)
Video
ITU-R-656
VMI 1.4
TV tuner
Controller
S Video
DVD
RIVA128ZX
45/85

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