STG3005A2S STMicroelectronics, STG3005A2S Datasheet - Page 40
STG3005A2S
Manufacturer Part Number
STG3005A2S
Description
128-BIT 3D MULTIMEDIA ACCELERATOR
Manufacturer
STMicroelectronics
Datasheet
1.STG3005A2S.pdf
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RIVA128ZX
Figure 40. SDRAM/SGRAM read to precharge, read latency of three
NOTE
Figure 41. SDRAM/SGRAM Write to Precharge
Figure 42. SDRAM/SGRAM Active to Read or Write
Table 12. SDRAM/SGRAM timing parameters
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Command
Symbol
t
t
t
t
t
t
FBD[63:0]
FBA[10:0]
CS
CH
MTC
RAS
RC
RCD
FBDQM#
FBCLKx
1 FBDQM is active (low)
Command
FBCSx, FBRAS#, FBCAS#, FBWE#,
FBDQM setup time
FBCSx, FBRAS#, FBCAS#, FBWE#,
FBDQM hold time
Load Mode register command to command
Active to Precharge command period
Active to Active command period
Active to Read or Write delay
FBCLKx
write data n
bank, col n
write
Command
FBA[10:0]
FBD[63:0]
FBCLKx
write data
Parameter
active
nop
n+1
bank,
col n
read
nop
t
WR
precharge nop
bank(s)
nop
precharge
bank(s)
t
RCD
128-BIT 3D MULTIMEDIA ACCELERATOR
t
RP
Min.
10
3
1
2
7
3
nop
nop
data n
nop
active
bank,
row
Max.
t
RP
read or write
nop
Unit
t
t
t
t
ns
ns
CK
CK
CK
CK
active
row
Notes
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