STG3005A2S STMicroelectronics, STG3005A2S Datasheet - Page 30
STG3005A2S
Manufacturer Part Number
STG3005A2S
Description
128-BIT 3D MULTIMEDIA ACCELERATOR
Manufacturer
STMicroelectronics
Datasheet
1.STG3005A2S.pdf
(85 pages)
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RIVA128ZX
6
The RIVA128ZX framebuffer interface supports SDRAM and SGRAM memory. Using SDRAM it can be
configured with an 8MByte 64-bit data bus. With SGRAM it can be configured with a 2 or 4MByte 64-bit
data bus or a 4 or 8MByte 128-bit data bus. The memory configurations supported by RIVA128ZX are
shown in Table 7. All of the framebuffer signalling environment is 3.3V.
Table 7. RIVA128ZX memory configurations
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FRAMEBUFFER INTERFACE
2MByte
4MByte
8MByte
2 banks of 4 devices
2 internal bank
2 devices
4 devices
SGRAM
128-bit
128-bit
8Mbit
64-bit
2 internal bank
2 devices
4 devices
SGRAM
16Mbit
128-bit
64-bit
N/A
128-BIT 3D MULTIMEDIA ACCELERATOR
4 internal bank
2 devices
4 devices
SGRAM
16Mbit
128-bit
64-bit
N/A
4 devices
1M x 16
SDRAM
16Mbit
64-bit
N/A
N/A
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