STG3005A2S STMicroelectronics, STG3005A2S Datasheet - Page 5

• Manufacturer Part Number: STG3005A2S
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

128-BIT 3D MULTIMEDIA ACCELERATOR
2
2.1
2.2
Signal
Signal
AGPADSTB0
AGPADSTB1
AGPST[2:0]
AGPRBF#
AGPPIPE#
PCICLK
PCIRST#
PCIAD[31:0]
PIN DESCRIPTIONS
ACCELERATED GRAPHICS PORT (AGP) INTERFACE
PCI 2.1 LOCAL BUS INTERFACE
I/O
I/O
I/O
I/O
O
O
I
I
I
Description
Description
AGP status bus providing information from the arbiter to the RIVA128ZX on what it may
do. AGPST[2:0] only have meaning to the RIVA128ZX when PCIGNT# is asserted. When
PCIGNT# is de-asserted these signals have no meaning and must be ignored.
Read Buffer Full indicates when the RIVA128ZX is ready to accept previously requested
low priority read data or not. When AGPRBF# is asserted the arbiter is not allowed to
return (low priority) read data to the RIVA128ZX. This signal should be pulled up via a
4.7K resistor (although it is supposed to be pulled up by the motherboard chipset).
Pipelined Read is asserted by RIVA128ZX (when the current master) to indicate a full
width read address is to be enqueued by the target. The RIVA128ZX enqueues one
request each rising clock edge while AGPPIPE# is asserted. When AGPPIPE# is de-
asserted no new requests are enqueued across PCIAD[31:0]. AGPPIPE# is a sustained
tri-state signal from the RIVA128ZX and is an input to the target (the core logic).
Bus strobe signals providing timing for AGP 2X data transfer mode on PCIAD[15:00] and
PCIAD[31:16] respectively. The agent that is supplying data drives these signals.
PCI clock. This signal provides timing for all transactions on the PCI bus, except for
PCIRST# and PCIINTA#. All PCI signals are sampled on the rising edge of PCICLK and
all timing parameters are defined with respect to this edge .
PCI reset. This signal is used to bring registers, sequencers and signals to a consistent
state. When PCIRST# is asserted all output signals are tristated.
32-bit multiplexed address and data bus. A bus transaction consists of an address phase
followed by one or more data phases.
000
001
010
011
100
101
110
111
Indicates that previously requested low priority read or flush data is being
returned to the RIVA128ZX.
Indicates that previously requested high priority read data is being returned to
the RIVA128ZX.
Indicates that the RIVA128ZX is to provide low priority write data for a previous
enqueued write command.
Indicates that the RIVA128ZX is to provide high priority write data for a previous
enqueued write command.
Reserved
Reserved
Reserved
Indicates that the RIVA128ZX has been given permission to start a bus transac-
tion. The RIVA128ZX may enqueue AGP requests by asserting AGPPIPE# or
start a PCI transaction by asserting PCIFRAME#. AGPST[2:0] are always an
output from the Core Logic (AGP chipset) and an input to the RIVA128ZX.
RIVA128ZX
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