STG3005A2S STMicroelectronics, STG3005A2S Datasheet - Page 39

• Manufacturer Part Number: STG3005A2S
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

128-BIT 3D MULTIMEDIA ACCELERATOR
Table 11. SDRAM/SGRAM I/O timing parameters
Figure 37. SDRAM/SGRAM random write cycles within a page
NOTE
Figure 38. SDRAM/SGRAM write to read cycle
NOTE
Figure 39. SDRAM/SGRAM read to precharge, read latency of two
NOTE
Symbol
t
t
HZ
DS
1 Covers either successive writes to the active row in a given bank or to the active rows in different banks. FBDQM is active
1 A read latency of 2 is shown for illustration
1 FBDQM is active (low)
(low).
Command
Command
FBA[10:0]
FBD[63:0]
FBA[10:0]
FBD[63:0]
FBCLKx
FBCLKx
Data out high impedance time
Write data setup time
Command
FBA[10:0]
FBD[63:0]
FBCLKx
write
data n
bank,
col n
write
bank, col n
Parameter
data n
write
write
data n
bank, col n
nop
read
bank, col a
data a
write
precharge
bank(s)
bank,
col b
read
nop
Min.
data n
4
4
bank, col x
t
nop
RP
data x
write
nop
read
data b
Max.
nop
10
bank,row
active
bank, col m
data m
write
nop
Unit
ns
ns
RIVA128ZX
Notes
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