STG3005A2S STMicroelectronics, STG3005A2S Datasheet - Page 53

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STG3005A2S

Manufacturer Part Number
STG3005A2S
Description
128-BIT 3D MULTIMEDIA ACCELERATOR
Manufacturer
STMicroelectronics
Datasheet
128-BIT 3D MULTIMEDIA ACCELERATOR
9
BIOS and initialization code for the RIVA128ZX is accessed from a 32KByte ROM. The RIVA128ZX mem-
ory bus interface signals FBD[15:0] and FBD[31:24] are used to address and access one of 64KBytes of
data respectively. The unique decode to the ROM device is provided by the ROMCS# chip select signal.
Figure 63. ROM interface
ROM interface timing specification
Figure 64. ROM interface timing diagram
BOOT ROM INTERFACE
WE# (FBD[17])
WE# (FBD[17])
OE# (FBD[16])
OE# (FBD[16])
RIVA128ZX
FDB[31:24]
FDB[31:24]
FDB[15:0]
FDB[15:0]
ROMCS#
ROMCS#
FBD[31:24]
FBD[15:0]
ROMCS#
ROM Read
ROM Write
FBD[17]
FBD[16]
t
BAS
t
BDBZ
t
BRV
t
BAS
t
BOS
t
BWDS
t
BWS
address
data
t
address
t
BRCS
BRCS
t
BOH
t
BWL
t
BDS
data
CS
A[15:0]
D[7:0]
WE
OE
t
BRH
t
t
BDH
BRCA
t
BWDH
t
t
BAH
BAH
t
BDZ
ROM
RIVA128ZX
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