S1D10605 Epson Electronics America, Inc., S1D10605 Datasheet - Page 101

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S1D10605

Manufacturer Part Number
S1D10605
Description
S1d15000 Series Lcd Driver With Ram
Manufacturer
Epson Electronics America, Inc.
Datasheet
Reset Circuit
The S1D15206 series chip parameters are initialized when both
SR1 and SR2 are set to low.
Rev.3.5
Initial parameter setup
1. Display
2. Duty cycle
3. ADC select
4. Read-modify-write
5. Power Control register
6. Initial Display Line register
7. Column Address counter
8. Page Address register
9. Register data of serial interface : Cleared
10. Electronic control register
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
COM 9
COM 10
COM 11
COM 12
COM 13
COM 14
COM 15
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
: Off
: 1/16 (S1D15206)
: Normal (D0 ADC com
: Off
: 0
: Line 1
: Address 0
: Page 0
: 0
mand is high and
ADC status flag is set)
COM -SEG 0
COM -SEG 1
COM 0
COM 1
COM 2
SEG 0
SEG 1
FR
0 1 2 3
0 1 2 3
EPSON
Figure 6
As explained in Section 4-32, the microprocessor should also be
reset when SR1 and SR2 are reset. The SR1 and SR2 go low only
when logical low pulses are entered at least 10 microseconds (refer
to Section for AC characteristics). The normal reset signal appears
1 microsecond after the rising edge of this signal.
If the on-board LCD power circuit of the S1D15206 series is not
used, both SR1 and SR2 must be low when an external LCD power
is supplied. If not low, the IC chip may be destroyed by surge
current. When reset, each register is cleared but the present setup of
oscillator circuit and output terminals (FR, CL, D0 to D7) is not
cleared.
As the S1D15206 series does not have a Power-On Clear circuit,
both SR1 and SR2 must go low when logic power applies. If not, any
recovery may fail.
The Reset command can reset parameters 6 to 10 listed above.
11. Static drive
12. Clock
16 0 1 2 3
32 0 1 2 3
: Off
: Output
S1D15206 Series
16
32
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
-V
-V
-V
-V
-V
V
V
V
V
V
V
-V
-V
-V
-V
-V
DD
SS
DD
1
2
3
4
5
DD
1
2
3
4
5
DD
1
2
3
4
5
DD
1
2
3
4
5
DD
1
2
3
4
5
5
4
3
2
1
DD
5
4
3
2
1
DD
1
2
3
4
5
1
2
3
4
5
4–17

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