S1D10605 Epson Electronics America, Inc., S1D10605 Datasheet - Page 217

• Manufacturer Part Number: S1D10605
• Description: S1d15000 Series Lcd Driver With Ram
• Manufacturer: Epson Electronics America, Inc.

S1D15600/601/602 Series
Chip select inputs
The S1D15600/601/602 series has two chip select pins:
CS1 and CS2, and data exchange between the microproc-
essor and the S1D15600/601/602 series is enabled when
CS1 is LOW and CS2 is HIGH. When these pins are set
to any other combination, D0 to D7 are high impedance.
The A0, RD, WR, SI and SCI inputs are disabled. If the
serial input interface has been selected, the shift register
and counter are reset. The Reset signal is entered
independent from the CS1 and CS2 status.
Data Transfer
To match the timing of the display data RAM and
registers to that of the controlling microprocessor, the
S1D15600/601/602 series uses an internal data bus and
bus buffer. A kind of pipeline processing takes place.
When the microprocessor reads the contents of RAM, the
data for the initial read cycle is first stored in the busbuffer
7–22
MPU
Internal
timing
CS1
CS2
SI
SCL
A0
WR
DATA
Bus
holder
WR
1
D7
2
N
D6
Figure 1. Serial interface timing
N
3
D5
Figure 2. Write timing
4
EPSON
D4
N+1
5
D3
(dummy read cycle). On the next read cycle, the data is
read from the bus buffer onto the microprocessor bus. At
the same time, the next block of data is transferred from
RAM to the bus buffer. Likewise, when the microproc-
essor writes data to display data RAM, the data is first
stored in the bus buffer before being written to RAM at
the next write cycle.
When writing data from the microprocessor to RAM,
there is no delay since data is automatically transferred
from the bus buffer to the display data RAM. If the data
rate is required to slow down, the microprocessor can
insert an NOP instruction which has the same affect as
executing a wait procedure.
When a sequence of address sets is executed, a dummy
read cycle must be inserted between each pair of address
sets. This is necessary because the addressed data from
the RAM is delayed one cycle by the bus buffer, before
it is sent to the microprocessor. A dummy read cycle is
thus necessary after an address set and after a write cycle.
N+1
6
D2
N+2
7
D1
N+2
8
D0
9
D7
N+3
10
D6
N+3
Rev. 4.6