S1D10605 Epson Electronics America, Inc., S1D10605 Datasheet - Page 454

• Manufacturer Part Number: S1D10605
• Description: S1d15000 Series Lcd Driver With Ram
• Manufacturer: Epson Electronics America, Inc.

S1D15710 Series
Display data latch circuit
The display data latch circuit is a latch that temporarily
stores the display data output from the display data
RAM to the liquid crystal drive circuit.
Since the Display Normal Rotation/Reversal, Display
ON/OFF, and Display All Lighting ON/OFF commands
control the data in this latch, the data within the display
data RAM is not changed.
Oscillator Circuit
This oscillator circuit is a CR type oscillator and generates
display clocks. The oscillator circuit is valid only when
M/S=HIGH and CLS=HIGH and starts oscillation after
the Built-in Oscillator Circuit ON command is entered.
When CLS=LOW, the oscillation is stopped and the
display clocks are entered from the CL pin.
Display Timing Generator Circuit
This display timing generator circuit generates timing
signals from the display clocks to the line address circuit
and the display latch circuit. It latches the display data
to the display data latch circuit and outputs it to the
segment drive output pin by synchronizing to the display
clocks. The read operation of display data to the liquid
crystal drive circuit is completely independent of the
access to the display data RAM from the MPU. Therefore
2-frame alternating current drive waveforms
11–16
Master
(M/S=HIGH)
Slave
(M/S=LOW)
COM0
COM1
SYNC
DATA
SEGn
RAM
FR
CL
Built-in oscillator circuit valid (CLS=HIGH)
Built-in oscillator circuit invalid (CLS=LOW)
Built-in oscillator circuit valid (CLS=HIGH)
Built-in oscillator circuit invalid (CLS=LOW)
Operation mode
64
65 1
2
3
4
5
6
EPSON
Figure 5
Table 5
60 61 62 63 64 65 1
even when the display data RAM is asynchronously
accessed during liquid crystal display, the access will
not have any adverse effect on the display such as
flickering.
The circuit also generates the internal common timing,
liquid crystal alternating current signal (FR), and
synchronous signal (SYNC) from the display clocks.
As shown in Figure 5, the FR normally generates the
drive waveforms in the 2-frame alternating current
drive system to the liquid crystal drive circuit. It can
generate n-line reversal alternating current drive
waveforms by setting data (n-1) to the n-line reversal
drive register. If a display quality problem such as
crosstalk occurs, it can be improved by using the n-line
reversal alternating current drive waveforms. Determine
the number of lines (n) to which alternating current is
applied by actually displaying the liquid crystal.
SNYC is a signal that synchronizes the line counter and
common timing generator circuit to the SYNC signal
output side IC. Therefore the SYNC signal becomes a
waveform at a duty ratio of 50% that synchronizes to the
frame synchronization.
When the S1D15710 series is used for the multiple chip
configuration, the slave side needs to supply the display
timing signals (FR, SYNC, CL, and DOF) from the
master side.
Table 5 shows the state of FR, SYNC, CL, or DOF.
Output
Output
Input
Input
FR
Output
Output
SYNC
Input
Input
2
3
4
Output
5
Input
Input
Input
CL
6
V
V
V
V
V
V
V
V
V
V
V
V
Rev. 1.1a
Output
Output
DD
1
4
5
DD
1
4
5
DD
2
3
5
DOF
Input
Input