S1D10605 Epson Electronics America, Inc., S1D10605 Datasheet - Page 68

• Manufacturer Part Number: S1D10605
• Description: S1d15000 Series Lcd Driver With Ram
• Manufacturer: Epson Electronics America, Inc.

S1D15210 Series
(7) Display Timing Generation Circuit
The master clock CL and the frame signal FR generate
internal timing. The master clock CL causes the line
counter to operate, which synchronizes with the line
(8) Display Data Latch Circuit
The display data latch circuit is a latch that temporarily
memorizes the display data to be output to the liquid
crystal drive circuit from the display data RAM for each
common period. Display ON/OFF and Display All
Lamps ON/OFF commands control the data in this latch.
Therefore, data in the display data RAM are never to be
modified.
(9) Liquid Crystal Drive Circuit
This circuit comprises 80 sets of multiplexers to generate
four-value level for the liquid crystal drive. Various
combinations of display data in the display data latch and
the FR signals output the liquid crystal waveforms as
shown in Fig. 3.
(10) Reset Circuit
This circuit detects the RES input rise or fall edge and
performs initialization.
RES input is level-sensed, then, as shown in Table 1, the
MPU interface mode is selected.
3–10
CL
Common driver
FR
EPSON
counter. Therefore, the master clock CL and the frame
signal FR input signals of the same phases as those of the
CR and FR signals of the common driver, respectively.
When connecting to MPU, the output port of MPU is
used and the reset signal is input through software.
Otherwise, the circuit is connected to the reset terminal
of MPU and the
input for 80-system MPU, and the
the 68-system MPU.
RES input causes initialization of S1D15210, and
initialization of the MPU is performed at the same time.
Failure of initialization by the RES terminal upon applying
power may lead to a status that cannot be released.
If the reset command is used, items 2 and 5 of the
following initial settings are to be executed:
(11) Status in Initial Setting
1. Display OFF
2. To set the display start line register on the first line.
3. Display All Lamps OFF
4. To set the column address counter to address 0.
5. To set the page address counter to the third page.
6. ADC select: normal rotation (ADC command = "0",
7. Read/Modify/Write OFF
ADC status flag "1")
CL
reset signal via the inverter is
S1D15210
FR
reset signal for
Rev. 1.1