XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 112

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Functional Description
Table 68: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
Powering Spartan-3E FPGAs
For additional information, refer to the “Powering Spartan-3
Generation FPGAs” chapter in UG331.
Voltage Supplies
Like Spartan-3 FPGAs, Spartan-3E FPGAs have multiple
voltage supply inputs, as shown in
Table 69: Spartan-3E Voltage Supplies
In a 3.3V-only application, all four V
3.3V. However, Spartan-3E FPGAs provide the ability to
bridge between different I/O voltages and standards by
applying different voltages to the V
112
Security
CRC
Persist
Option Name
VCCO_0
VCCO_1
VCCO_2
VCCO_3
V
Supply
V
Input
CCAUX
CCINT
Internal core supply voltage. Supplies all internal logic functions, such as CLBs,
block RAM, and multipliers. Input to Power-On Reset (POR) circuit.
Auxiliary supply voltage. Supplies Digital Clock Managers (DCMs), differential
drivers, dedicated configuration pins, JTAG interface. Input to Power-On Reset
(POR) circuit.
Supplies the output buffers in I/O Bank 0, the bank along the top edge of the
FPGA.
Supplies the output buffers in I/O Bank 1, the bank along the right edge of the
FPGA. In
connects to the same voltage as the Flash PROM.
Supplies the output buffers in I/O Bank 2, the bank along the bottom edge of the
FPGA. Connects to the same voltage as the FPGA configuration source. Input
to Power-On Reset (POR) circuit.
Supplies the output buffers in I/O Bank 3, the bank along the left edge of the
FPGA.
Pins/Function
reconfiguration
interface pins,
Configuration
Configuration
Slave mode,
SelectMAP,
SelectMAP
Readback,
BPI mode,
Affected
Partial
JTAG,
Byte-Wide Peripheral Interface (BPI) Parallel Flash
(default)
Enable
Disable
Values
Level1
Level2
None
Table
CCO
Yes
CCO
No
supplies connect to
69. There are two
inputs of different
Readback and limited partial reconfiguration are available via the JTAG port or via the
SelectMAP interface, if the Persist option is set to Yes.
Readback function is disabled. Limited partial reconfiguration is still available via the
JTAG port or via the SelectMAP interface, if the Persist option is set to Yes.
Readback function is disabled. Limited partial reconfiguration is disabled.
Default. Enable CRC checking on the FPGA bitstream. If error detected, FPGA
asserts INIT_B Low and DONE pin stays Low.
Turn off CRC checking.
All BPI and Slave mode configuration pins are available as user-I/O after configuration.
This option is required for Readback and partial reconfiguration using the SelectMAP
interface. The SelectMAP interface pins (see
configuration and are not available as user-I/O.
Description
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supply inputs for internal logic functions, V
V
supply input that powers the output buffers within the asso-
ciated I/O bank. All of the V
bank must be connected and must connect to the same
voltage.
banks. Refer to
can be intermixed within a single I/O bank.
Each I/O bank also has an separate, optional input voltage
reference supply, called V
CCAUX
. Each of the four I/O banks has a separate V
Description
I/O Banking Rules
Mode,
Slave Parallel
REF
CCO
. If the I/O bank includes an
connections to a specific I/O
DS312-2 (v3.6) May 29, 2007
Selectable, 3.3V, 2.5V,
Selectable, 3.3V, 2.5V,
Selectable, 3.3V, 2.5V,
Selectable, 3.3V, 2.5V,
Mode) are reserved after
for which I/O standards
1.8, 1.5V, or 1.2V
1.8, 1.5V, or 1.2V
1.8, 1.5V, or 1.2V
1.8, 1.5V, or 1.2V
Nominal Supply
Product Specification
Voltage
1.2V
2.5V
CCINT
CCO
and
R