XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 156

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

DC and Switching Characteristics
Serial Peripheral Interface (SPI) Configuration Timing
Table 117: Timing for Serial Peripheral Interface (SPI) Configuration Mode
156
(Open-Drain)
T
T
T
T
T
T
T
PROG_B
CCLK1
CCLKn
MINIT
INITM
CCO
DCC
CCD
Symbol
HSWAP
VS[2:0]
CSO_B
INIT_B
M[2:0]
CCLK
MOSI
(Input)
(Input)
(Input)
(Input)
(Input)
DIN
Shaded values indicate specifications on attached SPI Flash PROM.
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on VS[2:0] and M[2:0] mode pins before the rising
edge of INIT_B
Hold time on VS[2:0] and M[2:0]mode pins after the rising edge of
INIT_B
MOSI output valid after CCLK edge
Setup time on DIN data input before CCLK edge
Hold time on DIN data input after CCLK edge
T
MINIT
Figure 77: Waveforms for Serial Peripheral Interface (SPI) Configuration
Pin initially pulled High by internal pull-up resistor if HSWAP input is Low.
Pin initially high-impedance (Hi-Z) if HSWAP input is High. External pull-up resistor required on CSO_B.
<1:1:1>
<0:0:1>
HSWAP must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
T
CCLK1
Description
T
CSS
Command
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
(msb)
T
www.xilinx.com
CCO
T
DSU
T
MCCL1
Command
(msb-1)
T
MCCH1
T
DH
Minimum
Data
50
0
(see
(see
T
See
See
See
New ConfigRate active
T
CCLK1
DS312-3 (v3.6) May 29, 2007
MCCL n
Data
T
T
Maximum
V
Table
Table
Table 115
Table 115
Table 115
DCC
Product Specification
-
-
111)
111)
Data
T
CCD
ds312-3_06_110206
T
CCLK n
T
MCCH n
Units
ns
ns
Data
R