XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 99

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Slave Serial Mode
For additional information, refer to the “Slave Serial Mode”
chapter in UG332.
In Slave Serial mode (M[2:0] = <1:1:1>), an external host
such as a microprocessor or microcontroller writes serial
configuration data into the FPGA, using the synchronous
serial interface shown in
data is presented on the FPGA’s DIN input pin with suffi-
cient setup time before each rising edge of the externally
generated CCLK clock input.
DS312-2 (v3.6) May 29, 2007
Product Specification
•
•
•
•
Internal memory
Disk drive
Over network
Over RF link
Configuration
Memory
Source
Download Host
Intelligent
R
Recommend
open-drain
PROG_B
•
•
•
Microcontroller
Processor
Tester
driver
READ/WRITE
DATA[7:0]
VCC
GND
PROG_B
SELECT
V
CLOCK
INIT_B
TMS
TCK
TDO
DONE
BUSY
TDI
JTAG
2.5V
Figure
63. The serial configuration
Figure 62: Daisy-Chaining using Slave Parallel Mode
Parallel
Slave
Mode
P
‘1’
‘1’
‘0’
‘0’
HSWAP
M2
M1
M0
D[7:0]
BUSY
CSI_B
RDWR_B
CCLK
TDI
TMS
TCK
PROG_B
Spartan-3E
VCCINT
+1.2V
FPGA
GND
VCCAUX
VCCO_0
VCCO_1
VCCO_2
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CSO_B
INIT_B
DONE
LDC0
LDC1
LDC2
HDC
TDO
VCCO_0
VCCO_1
+2.5V
V
V
The intelligent host starts the configuration process by puls-
ing PROG_B and monitoring that the INIT_B pin goes High,
indicating that the FPGA is ready to receive its first data.
The host then continues supplying data and clock signals
until either the DONE pin goes High, indicating a successful
configuration, or until the INIT_B pin goes Low, indicating a
configuration error. The configuration process requires
more clock cycles than indicated from the configuration file
size. Additional clocks are required during the FPGA’s
start-up sequence, especially if the FPGA is programmed to
wait for selected Digital Clock Managers (DCMs) to lock to
their respective clock inputs (see
+2.5V
Parallel
Slave
Mode
P
‘1’
‘1’
‘0’
‘0’
HSWAP
M2
M1
M0
D[7:0]
BUSY
CSI_B
RDWR_B
CCLK
TDI
PROG_B
TMS
TCK
Spartan-3E
VCCINT
FPGA
+1.2V
GND
VCCAUX
VCCO_0
VCCO_1
VCCO_2
CSO_B
Start-Up, page
INIT_B
DONE
Functional Description
LDC0
LDC1
LDC2
HDC
TDO
VCCO_0
VCCO_1
+2.5V
V
DS312-2_53_022305
108).
D[7:0]
CCLK
CSO_B
PROG_B
DONE
INIT_B
TMS
TCK
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