HD49338F Renesas Electronics Corporation., HD49338F Datasheet - Page 8

• Manufacturer Part Number: HD49338F
• Description: Cds/pga & 12-bit A/d Converter
• Manufacturer: Renesas Electronics Corporation.

HD49338F/HF
Internal Functions
Functional Description
CDS input
ADC input
Y-IN input
Automatic offset calibration of PGA and ADC
DC offset compensation feedback for CCD and CDS
Pre-blanking
Digital output enable function
Note: 1. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
Operating Description
Figure 1 shows CDS/PGA + ADC function block.
1. CDS (Correlated Double Sampling) Circuit
Rev.2.00 May 20, 2005 page 6 of 22
CCD low-frequency noise is suppressed by CDS (correlated double sampling).
The signal level is clamped at 56 LSB to 304 LSB by resister during the OB period.
Gain can be adjusted using 10 bits of register (0.033 dB steps) within the range from –2.36 dB to 31.40 dB. *
The center level of the input signal is clamped at 2048 LSB (Typ).
Gain can be adjusted using 10 bits of register (0.00446 times steps) within the range from 0.57 times (–4.86 dB) to
The input signal is clamped at 280 LSB (Typ) by SYNC Tip clamp.
CDS input operation is protected by separating it from the large input signal.
Digital output is fixed at 32 LSB.
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The
black level is directly sampled at C1 by using the SPBLK pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly sampled at C2 by using the SPSIG pulse, and provided to CDSAMP (see figure 1). The
difference between these two signal levels is extracted by the CDSAMP, which also operates as a programmable
gain amplifier at the previous stage. The CDS input is biased with VRT (2 V) during the SPBLK pulse validation
period. During the PBLK period, the above sampling and bias operation are paused.
5.14 times (14.22 dB). *
CDSIN
VRT
BLKFB
C1
C2
1
Figure 1 HD49338F/HF Functional Block Diagram
SH
AMP
C3
CDS
AMP
BLKSH
Gain setting
(register)
Current
ADCIN
DAC
C4
BLKC
PG
AMP
DAC
Clamp data
(register)
12-bit
ADC
calibration
DC offset
feedback
Offset
OBP
logic
logic
D0 to D11
1