HD49338F Renesas Electronics Corporation., HD49338F Datasheet - Page 16

• Manufacturer Part Number: HD49338F
• Description: Cds/pga & 12-bit A/d Converter
• Manufacturer: Renesas Electronics Corporation.

HD49338F/HF
Explanation of Serial Data of CDS Part
Serial data of CDS part has the following functions.
PGA gain (D5 to D12 of register 0)
CSEL (D15 of register 0)
SLP and STBY (D3, D4 of register 1)
Output mode (D5 to D7 of register 1 and D4 of register 3)
SHA-fsel (D8 to D9 of register 1)
SHSW-fsel (D10 to D13 of register 1)
Rev.2.00 May 20, 2005 page 14 of 22
1
Details are referred to page 6 block diagram.
Above PGA gain definition means input signal 1 Vp-p to CDS_in, and set N = 18 (correspond 2.36 dB), and then
PGA outputs the 2 V full-range, and also ADC out puts the full code (1023).
This mean offset gain of PGA has 6 dB – 2.36 dB = 3.64 dB, therefore it should be decided that how much dB add
on.
SLP:
STBY: Only the standard voltage generating circuit is operated. Consumption current of CDS part is about 3 mA.
It is a test mode. Combination details are table 3 to 5. Normally set to all 0.
It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 9. To get rough idea, set the
double cut off frequency point with using.
It is a time constant which sampling the black level of SH amplifier. Frequency characteristics are referred to page
9. To get rough idea, set the double cut off frequency point with using. S/N changes by this data, so find the
appropriate point with set data to up/down.
1
At CDS_in mode: –2.36 dB + 0.132 dB × N (Log linear)
At ADC_in mode: 0.57 times + 0.01784 times × N (Times linear)
∗: Full-scale digital output is defined as 0 dB when 1 V is input.
Data = 0: Select CDSIN
Data = 1: Select ADCIN
1
Stop the all circuit. Consumption current of CDS part is less than 10 µA.
Start up from offset calibration when recover is needed.
Allow 50 H time for feedback clamp is stabilized until recover.
Address
1
0
0
0
(1.0 V)
1
0 dB when set N = 18 which correspond to 2.36 dB
(CDS = 0 dB)
Figure 9 Level Dia of PGA
CDS
CDS
(2) Level dia on the circuit
3.64 dB + 0.132 dB
(1) Level dia explain
(1.0 V)
STD1[7:0] (L)
D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
PGA
PGA
(2.0 V)
N
ADC
ADC
2 V
(1023)
test_I2
1023
STD2[15:8] (H)
SHSW_fsel
SHA_fsel