HD49338F Renesas Electronics Corporation., HD49338F Datasheet - Page 10

• Manufacturer Part Number: HD49338F
• Description: Cds/pga & 12-bit A/d Converter
• Manufacturer: Renesas Electronics Corporation.

HD49338F/HF
6. ADC Digital Output Control Function
Table 3
Table 4
Table 5
Rev.2.00 May 20, 2005 page 8 of 22
Notes: 1. STBY, TEST, LINV, and MINV are set by register.
Output Pin
Output
codes
Output Pin
Output
codes
H
L
The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5
show the output functions and the codes.
H
X
L
2. Mode setting for the OEB and the PBLK are done by external input pins.
3. The polarity of the PBLK pin when the register setting is SPinv is low.
Steps
Steps
X
X
H
L
ADC Digital Output Functions
ADC Output Code
ADC Output Code (TEST1)
X
X
H
X
L
2047
2048
4092
4093
4094
4095
2047
2048
4092
4093
4094
4095
0
1
2
3
4
5
6
0
1
2
3
4
5
6
X
X
H
H
X
H
H
X
H
H
L
L
L
L
L
L
D11
D11
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
H
H
X
H
H
X
H
H
L
L
L
L
L
L
X
X
H
H
H
H
H
H
H
H
X
X
X
X
L
L
D10
D10
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Hi-Z
Hi-Z
Same as in table 4.
D11 is inverted in table 4.
D10 to D0 are inverted in table 4.
D11 to D0 are inverted in table 4.
Output code is set up to Clamp Level.
Same as in table 5.
D11 is inverted in table 5.
D10 to D0 are inverted in table 5.
D11 to D0 are inverted in table 5.
Output code is set up to Clamp Level.
D11 D10
H
H
L
L
D9
D9
H
H
L
L
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D9
H
H
L
L
D8
D8
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D8
H
H
L
L
ADC Digital Output
D7
H
H
L
L
D7
D7
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D6
H
H
L
L
D6
D6
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D5
H
H
L
L
D4
H
H
L
L
D5
D5
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D3
H
H
L
L
D2
D4
D4
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D1
H
H
L
L
D3
D3
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D0
H
H
L
L
Low-power wait state
Output Hi-Z
Normal operation
Pre-blanking
Normal operation
Pre-blanking
Test mode
D2
D2
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Operating Mode
D1
D1
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D0
D0
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L