HD49338F Renesas Electronics Corporation., HD49338F Datasheet - Page 17

• Manufacturer Part Number: HD49338F
• Description: Cds/pga & 12-bit A/d Converter
• Manufacturer: Renesas Electronics Corporation.

HD49338F/HF
Clamp (D3 to D7 of register 2)
HGstop-Hsel, HGain-Nsel (D8 to D11 of register 2)
Low_PWR (D12 of register 2)
SPinv (D13 of register 2)
Reset (D15 of register 2)
C_Bias_off (D3 of register 3)
Ave_4H (D6 of register 3)
Differential Code and Gray Code (D4 to D5 and D7 to D9 of register 3)
Gray code (D4 to D5 of register 3)
Serial data setting items (D7 to D9 of register 3)
Rev.2.00 May 20, 2005 page 15 of 22
Determine the OB part level with digital code of ADC output.
Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch
the high speed leading mode. Transfer the gain +1/–1 to previous field, its switch to high speed leading mode.
Switch circuit current and frequency characteristic.
SPSIG/SPBLK/PBLK input signal inverted switching.
Software reset.
Offset calibration should be done when starting up with using this bit. Details are referred to page 19.
Center bias is turned off in ADCIN mode.
Clamp detection data is averaged 4H.
DC output code can be change to following type.
Gray Code [1]
0
0
1
1
Setting Bit
Gray_test[0]
Gray_test[1]
Gray_test[2]
• Standard data output timing
Gray_test[1]
Low
Low
High
High
Clamp level = setting data × 2 + 14
Default data is 9 = 32 LSB.
Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee
Data = 1: Normal
Data = 0: Inverted
Data = 1: Normal
Data = 0: Reset
Data = 0: Normally on
Data = 1: Off
Data = 0: 1H
Data = 1: Averaged 4H
Gray Code [0]
0
1
0
1
Standard data output timing control signal
(Refer to the following table)
ADCLK polar with OBP. (Lo→Positive edge, HI→Negative edge)
Setting Contents
Gray_test[0]
Low
High
Low
High
Output Code
Binary code
Gray code
Differential encoded binary
Differential encoded gray
Standard Data Output Timing
Third and fourth
Fourth and fifth
Fifth and sixth
Sixth and seventh