HD49338F Renesas Electronics Corporation., HD49338F Datasheet - Page 21

• Manufacturer Part Number: HD49338F
• Description: Cds/pga & 12-bit A/d Converter
• Manufacturer: Renesas Electronics Corporation.

HD49338F/HF
Operation Sequence at Power On
Rev.2.00 May 20, 2005 page 19 of 22
V
Start control
of TG and
camera DSP
OBP
HD49338F/HF
serial data transfer
RESET bit
Automatic offset
calibration
The following describes the above serial data transfer. For details on registers 0, 1, and 2, refer to table 10.
DD
(1) Register 2 setting
(2) Register 2 setting
(3) Register 0 and 1 settings
(4) Please perform an offset calibration in the period which avoided PBLK of V.
SPBLK
SPSIG
ADCLK
etc.
: Set all bits in register 2 to the usage condition, and set the RESET bit to low.
: Cancel the RESET mode by setting the register 2 RESET bit to high.
: After the offset calibration is terminated, set registers 0 and 1.
Do not change other register 2 settings. Offset calibration starts automatically.
Must be stable within the operating
power supply voltage range
Prohibition
period
(1) Register 2 setting
RESET = "Low"
(RESET mode)
OBP is started within this period
2 ms or more
2 ms or more
1 ms or more
(2) Register 2 setting
(4)Offset calibration
(automatically starts
cancellation)
(RESET cancellation)
Ends after
40000 clock cycles
after RESET
RESET = "High"
High-speed pulse is the right phase
0 ms
or more
OBP is the right phase
(3) Registers 0
and 1 settings