HD49338F Renesas Electronics Corporation., HD49338F Datasheet - Page 12

• Manufacturer Part Number: HD49338F
• Description: Cds/pga & 12-bit A/d Converter
• Manufacturer: Renesas Electronics Corporation.

HD49338F/HF
Timing Chart
Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
The ADC output (D0 to D11) is output at the rising edge of the ADCLK in both modes.
Pipe-line delay is twelve clock cycles when CDSIN is used and eleven when ADCIN is used.
In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.
Rev.2.00 May 20, 2005 page 10 of 22
CDSIN
SPBLK
SPSIG
ADCLK
D0 to D11
ADCIN
ADCLK
D0 to D11
Note: The phases of SPBLK and SPSIG are those when the serial data SPinv bit is set to low.
When CDSIN input mode is used
When ADCIN input mode is used
Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used
N
0
N 11
N
N 12
N+1
1
N 10
N+1
N 11
N+2
2
N+2
N 10
N+10
~
N 1
N+11
11
N+11
N
N 1
N+12
12
N+12
N+1
N
N+13
13
N+13