DSPIC33FJ64MC508 Microchip Technology Inc., DSPIC33FJ64MC508 Datasheet - Page 257

• Manufacturer Part Number: DSPIC33FJ64MC508
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

REGISTER 21-2:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12-11
bit 10
bit 9-8
bit 7
bit 6
bit 5-2
bit 1
bit 0
R/W-0
BUFS
R-0
VCFG<2:0>: Converter Voltage Reference Configuration bits
Unimplemented: Read as ‘0’
CSCNA: Scan Input Selections for CH0+ during Sample A bit
1 = Scan inputs
0 = Do not scan inputs
CHPS<1:0>: Selects Channels Utilized bits
When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’
1x = Converts CH0, CH1, CH2 and CH3
01 = Converts CH0 and CH1
00 = Converts CH0
BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1 = ADC is currently filling second half of buffer, user should access data in the first half
0 = ADC is currently filling first half of buffer, user should access data in the second half
Unimplemented: Read as ‘0’
SMPI<3:0>: Selects Increment Rate for DMA Addresses bits or number of sample/conversion
operations per interrupt.
1111 = Increments the DMA address or generates interrupt after completion of every 16th
1110 = Increments the DMA address or generates interrupt after completion of every 15th
•
•
•
0001 = Increments the DMA address or generates interrupt after completion of every 2nd
0000 = Increments the DMA address or generates interrupt after completion of every
BUFM: Buffer Fill Mode Select bit
1 = Starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt
0 = Always starts filling buffer from the beginning
ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample A on first sample and Sample B on next sample
0 = Always uses channel input selects for Sample A
VCFG<2:0>
000
001
010
011
1xx
dsPIC33FJXXXMCX06/X08/X10 MOTOR CONTROL FAMILY
R/W-0
U-0
—
ADxCON2: ADCx CONTROL REGISTER 2 (where x = 1 or 2)
sample/conversion operation
sample/conversion operation
sample/conversion operation
sample/conversion operation
External V
External V
ADREF+
A
A
A
W = Writable bit
‘1’ = Bit is set
VDD
VDD
VDD
R/W-0
R/W-0
REF
REF
+
+
External V
External V
ADREF-
R/W-0
Avss
Avss
Avss
U-0
—
SMPI<3:0>
REF
REF
-
-
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
CSCNA
R/W-0
R/W-0
x = Bit is unknown
R/W-0
R/W-0
BUFM
CHPS<1:0>
DS70287A-page 255
R/W-0
R/W-0
ALTS
bit 8
bit 0