DSPIC33FJ64MC508 Microchip Technology Inc., DSPIC33FJ64MC508 Datasheet - Page 78

• Manufacturer Part Number: DSPIC33FJ64MC508
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC33FJXXXMCX06/X08/X10 MOTOR CONTROL FAMILY
TABLE 5-1:
5.1
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in Table 5-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 8.0 for further details.
TABLE 5-2:
DS70287A-page 76
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>
POR (RCON<0>)
Note:
Reset Type
WDTR
MCLR
SWR
POR
BOR
Clock Source Selection at Reset
All Reset flag bits may be set or cleared by the user software.
Flag Bit
Oscillator Configuration bits
(FNOSC<2:0>)
COSC Control bits
(OSCCON<14:12>)
RESET FLAG BIT OPERATION
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
Trap conflict event
Illegal opcode or uninitialized
W register access
MCLR Reset
RESET instruction
WDT time-out
PWRSAV #SLEEP instruction
PWRSAV #IDLE instruction
BOR
POR
Setting Event
5.2
The Reset times for various types of device Reset are
summarized in Table 5-3. The system Reset signal,
SYSRST, is released after the POR and PWRT delay
times expire.
The time at which the device actually begins to execute
code also depends on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
Device Reset Times
—
POR
POR
POR
POR
PWRSAV instruction, POR
POR
POR
—
© 2007 Microchip Technology Inc.
Clearing Event