DSPIC33FJ64MC508 Microchip Technology Inc., DSPIC33FJ64MC508 Datasheet - Page 335

• Manufacturer Part Number: DSPIC33FJ64MC508
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

O
Open-Drain Configuration ................................................. 148
Output Compare ............................................................... 159
P
Packaging ......................................................................... 323
Peripheral Module Disable (PMD) .................................... 146
PICSTART Plus Development Programmer ..................... 282
Pinout I/O Descriptions (table) ............................................ 15
POR and Long Oscillator Start-up Times............................ 77
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
Power-Saving Features .................................................... 145
Program Address Space ..................................................... 29
Program Memory
Pulse-Width Modulation Mode .......................................... 160
PWM
PWM Dead-Time Generators ........................................... 168
© 2007 Microchip Technology Inc.
Registers................................................................... 162
Details ....................................................................... 324
Marking ..................................................................... 323
Register Map............................................................... 54
Register Map............................................................... 54
Register Map............................................................... 55
Register Map............................................................... 55
Register Map............................................................... 55
Register Map............................................................... 55
Register Map............................................................... 56
Clock Frequency and Switching................................ 145
Construction................................................................ 62
Data Access from Program Memory Using
Data Access from Program Memory Using Table
Data Access from, Address Generation...................... 63
Memory Map ............................................................... 30
Table Read Instructions
Visibility Operation ...................................................... 65
Interrupt Vector ........................................................... 31
Organization................................................................ 31
Reset Vector ............................................................... 31
Center-Aligned .......................................................... 167
Complementary Mode............................................... 168
Complementary Output Mode................................... 169
Duty Cycle................................................................. 160
Edge-Aligned ............................................................ 166
Independent Output Mode ........................................ 169
Operation During CPU Idle Mode ............................. 171
Operation During CPU Sleep Mode.......................... 171
Output Override ........................................................ 169
Output Override Synchronization.............................. 170
Period................................................................ 160, 166
Single Pulse Mode .................................................... 169
Assignment ............................................................... 169
Ranges...................................................................... 169
Selection Bits (table) ................................................. 169
Program Space Visibility ..................................... 65
Instructions ......................................................... 64
TBLRDH ............................................................. 64
TBLRDL .............................................................. 64
dsPIC33FJXXXMCX06/X08/X10 MOTOR CONTROL FAMILY
PWM Duty Cycle
PWM Fault Pins ................................................................ 170
PWM Output and Polarity Control..................................... 170
PWM Special Event Trigger.............................................. 171
PWM Time Base............................................................... 165
PWM Update Lockout....................................................... 171
Q
QEI
Quadrature Encoder Interface (QEI)................................. 185
Quadrature Encoder Interface (QEI) Module
R
Reader Response............................................................. 338
Registers
Comparison Units ..................................................... 167
Immediate Updates .................................................. 167
Register Buffers........................................................ 167
Enable Bits ............................................................... 170
Fault States .............................................................. 170
Input Modes.............................................................. 171
Priority ...................................................................... 170
Output Pin Control .................................................... 170
Postscaler................................................................. 171
Continuous Up/Down Count Modes ......................... 165
Double Update Mode................................................ 166
Free-Running Mode.................................................. 165
Postscaler................................................................. 166
Prescaler .................................................................. 166
Single-Shot Mode ..................................................... 165
16-bit Up/Down Position Counter Mode ................... 186
Alternate 16-bit Timer/Counter ................................. 187
Count Direction Status.............................................. 186
Error Checking.......................................................... 186
Interrupts .................................................................. 188
Logic ......................................................................... 186
Operation During CPU Idle Mode............................. 187
Operation During CPU Sleep Mode ......................... 187
Position Measurement Mode.................................... 186
Programmable Digital Noise Filters .......................... 187
Timer Operation During CPU Idle Mode................... 188
Timer Operation During CPU Sleep Mode ............... 187
Register Map .............................................................. 44
ADxCHS0 (ADCx Input Channel 0 Select ................ 259
ADxCHS123 (ADCx Input Channel 1, 2, 3 Select) ... 258
ADxCON1 (ADCx Control 1) .................................... 253
ADxCON2 (ADCx Control 2) .................................... 255
ADxCON3 (ADCx Control 3) .................................... 256
ADxCON4 (ADCx Control 4) .................................... 257
ADxCSSH (ADCx Input Scan Select High) .............. 260
ADxCSSL (ADCx Input Scan Select Low)................ 260
ADxPCFGH (ADCx Port Configuration High) ........... 261
ADxPCFGL (ADCx Port Configuration Low) ............ 261
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer) .......... 236
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer) .......... 237
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer) ........ 237
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer) ...... 238
CiCFG1 (ECAN Baud Rate Configuration 1)............ 234
CiCFG2 (ECAN Baud Rate Configuration 2)............ 235
CiCTRL1 (ECAN Control 1) ...................................... 226
CiCTRL2 (ECAN Control 2) ...................................... 227
CiEC (ECAN Transmit/Receive Error Count) ........... 233
CiFCTRL (ECAN FIFO Control) ............................... 229
CiFEN1 (ECAN Acceptance Filter Enable)............... 236
Cycle-by-Cycle ................................................. 171
Latched............................................................. 171
DS70287A-page 333