MBM29LV320TE80TN Meet Spansion Inc., MBM29LV320TE80TN Datasheet - Page 34

• Manufacturer Part Number: MBM29LV320TE80TN
• Description: Flash Memory Cmos 32 M 4 M ? 8/2 M ? 16 Bit
• Manufacturer: Meet Spansion Inc.

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MBM29LV320TE/BE
13. DQ
Data Polling
14. DQ
Toggle Bit I
15. DQ
Exceeded Timing Limits
The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm an attempt to read the device produces a
complement of data last written to DQ
read device produces true data last written to DQ
device produces a “0” at the DQ
device produces a “1” on DQ
( ■FLOW CHART).
For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased,
not a protected sectors. Otherwise, the status may be invalid.
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ
asynchronously while the output enable (OE) is asserted low. This means that the device is driving status
information on DQ
when the system samples the DQ
the Embedded Algorithm operation and DQ
The valid data on DQ
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algo-
rithm, Erase Suspend mode or sector erase time-out. (See “Hardware Sequence Flags” Table.)
See “6. Data Polling during Embedded Algorithm Operation Timing Diagram” in ■TIMING DIAGRAM for the
Data Polling timing specifications and diagrams.
The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data
from the device results in DQ
cycle is completed, DQ
ming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For
chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write
pulse sequence. The Toggle Bit I is active during the sector time out.
In program operation, if the sector being written to be protected, the toggle bit toggles for about 1 μs and then
stops toggling with data unchanged. In erase operation, the device erases all selected sectors except for ones
that are protected. If all selected sectors are protected, chip toggles the toggle bit for about 400 μs and then
drop back into read mode, having data unchanged.
Either CE or OE toggling causes DQ
See “7. Toggle Bit I during Embedded Algorithm Operation Timing Diagram” in ■TIMING DIAGRAM for the
Toggle Bit I timing specifications and diagrams.
DQ
conditions DQ
not successfully completed. Data Polling is the only operating function of device under this condition. The CE
circuit partially powers down device under these conditions (to approximately 2 mA) . The OE and WE pins
5
indicates if the program or erase time has exceeded the specified limits (internal pulse count) . Under these
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6
5
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produces a “1”. This is a failure condition which indicates that the program or erase cycle was
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at one instant of time and then that byte’s valid data the next instant of time. Depending on
0
to DQ
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stops toggling and valid data is read on the next successive attempts. During program-
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7
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. The flowchart for Data Polling (DQ
toggling between one and zero. Once the Embedded Program or Erase Algorithm
will be read on the successive read attempts.
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output. Upon completion of the Embedded Erase Algorithm an attempt to read
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output, it may read the status or valid data. Even if the device has completed
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Retired Product DS05-20894-5E_July 31, 2007
to toggle.
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. Upon completion of the Embedded Program Algorithm, an attempt to
80/90/10
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has a valid data, the data outputs on DQ
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. During the Embedded Erase Algorithm, an attempt to read
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) is shown in “3. Data Polling Algorithm”
0
to DQ
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may be still invalid.
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) may change