MBM29LV320TE80TN Meet Spansion Inc., MBM29LV320TE80TN Datasheet - Page 36

• Manufacturer Part Number: MBM29LV320TE80TN
• Description: Flash Memory Cmos 32 M 4 M ? 8/2 M ? 16 Bit
• Manufacturer: Meet Spansion Inc.

36
MBM29LV320TE/BE
*1 : Successive reads from the erasing or erase-suspend sector cause DQ
*2 : Reading from non-erase suspend sector address indicates logic “1” at the DQ
19. RY/BY
Ready/Busy
20. Byte/Word Configuration
21. Data Protection
Program
Erase
Erase-Suspend Read
Erase-Suspend Program
(Erase-Suspended Sector)
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
gone high. The system may continue to monitor the toggle bit and DQ
mining the status as described in the previous paragraph. Alternatively, the system may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine
the status of the operation. See “4. Toggle Bit Algorithm” in ■FLOW CHART.
The device provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded
Algorithms are either in progress or has been completed. If output is low, the device is busy with either a program
or erase operation. If output is high, the device is ready to accept any read/write or erase operation. When the
RY/BY pin is low, the device will not accept any additional program or erase commands. If the device is placed
in an Erase Suspend mode, RY/BY output is high.
During programming, RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, RY/BY pin is driven low after the rising edge of the sixth write pulse. RY/BY pin indicates a busy
condition during RESET pulse. See “9. RY/BY Timing Diagram during Program/Erase operations” and “10.
RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM for a detailed timing diagram. RY/BY pin is pulled high
in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to V
be connected to the host system via more than one RY/BY pin in parallel.
BYTE pin selects byte (8-bit) mode or word (16-bit) mode for device. When this pin is driven high, the device
operates in word (16-bit) mode. Data is read and programmed at DQ
device operates in byte (8-bit) mode. Under this mode, DQ
to DQ
are written at DQ
Diagram”, “12. Byte Mode Configuration Timing Diagram” and “13. BYTE Timing Diagram for Write Operations”
in ■TIMING DIAGRAM the detail .
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transitions. During power up device automatically resets internal state
machine in Read mode. Also, with its control register architecture, alteration of memory contents only occurs
after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from V
and power-down transitions or system noise.
8
bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands
Mode
15
to DQ
8
and the DQ
Retired Product DS05-20894-5E_July 31, 2007
7
80/90/10
Toggle Bit Status Table
to DQ
DQ
DQ
DQ
0
1
7
7
7
0
bits are ignored. See “11. Word Mode Configuration Timing
15
/A
-1
pin becomes the lowest address bit, and DQ
Toggle
Toggle
Toggle
15
DQ
5
1
to DQ
through successive read cycles, deter-
2
6
to toggle.
0
. When this pin is driven low, the
2
bit.
CC
; multiples of devices may
Toggle*
Toggle
DQ
1*
1
2
CC
2
power-up
1
5
has not
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