MBM29PL3200BE Fujitsu Microelectronics, Inc., MBM29PL3200BE Datasheet - Page 22

• Manufacturer Part Number: MBM29PL3200BE
• Description: Page Mode Flash Memory 32 M 2 M X 16/1 M X 32 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

22
MBM29PL3200TE/BE
Read/Reset Command
Autoselect Command
Word/Double Word Programming
COMMAND DEFINITIONS
The device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in an improper sequence will reset the device to the
read mode. Table 4 defines the valid register command sequences. Note that the Erase Suspend (B0h) and
Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover both
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that
commands are always written at DQ
In order to return from Autoselect mode or Exceeded Timing Limits (DQ
Reset operation is initiated by writing the Read/Reset command sequence into the command register. Micro-
processor read cycles retrieve array data from the memory. The device remains enabled for reads until the
command register contents are altered.
The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Character-
istics and Waveforms for specific timing parameters.
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
both manufacture and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming method-
ology. The operation is initiated by writing the Autoselect command sequence into the command register. Fol-
lowing the last command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read
cycle at address XX01h (XX02h for 8) returns 7Eh indicating that this device uses an extended device code.
The successive read cycle from XX0Eh to XX0Fh returns this extended device code for this device. (See Tables
5.1 to 5.4.)
The sector state (protection or unprotection) will be indicated by address XX02h for
Scanning the sector addresses (A
will produce a logical “1” at device output DQ
margin mode verification on the protected sector. (See Tables 2 and 3.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and to
write the Autoselect command during the operation by executing it after writing the Read/Reset command
sequence.
The device is programmed on a word-by-word (or double word-by-double word) basis. Programming is a four
bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command
and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later, and the
data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE
(whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command
sequence, the system is not required to provide further controls or timings. The device will automatically provide
adequate internally generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)
The system can determine the status of the program operation by using DQ
The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.
The automatic programming operation is completed when the data on DQ
bit. Then, the device return to the read mode and addresses are no longer latched. (See Table 10, Hardware
Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time.
Hence, Data Polling must be performed at the memory location which is being programmed.
19
, A
15
18
to DQ
, A
17
0
70/90
, A
for a protected sector. The programming verification should perform
0
and DQ
16
, A
15
, A
31
14
to DQ
, A
13
16
and A
9
bits are ignored.
to a high voltage. However, multiplexing high
12
) while (A
5
7
7
1) to Read/Reset mode, the Read/
is equivalent to data written to this
(Data Polling), or DQ
6
, A
3
, A
2
, A
32 (XX04h for
1
, A
0
)
(0, 0, 0, 1, 0)
6
(Toggle Bit).
16).