MBM29PL3200BE Fujitsu Microelectronics, Inc., MBM29PL3200BE Datasheet - Page 30

• Manufacturer Part Number: MBM29PL3200BE
• Description: Page Mode Flash Memory 32 M 2 M X 16/1 M X 32 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

30
MBM29PL3200TE/BE
Reading Toggle Bits DQ
Note : Successive reads from the erasing or erase-suspend sector will cause DQ
Double Word/Word Configuration
Data Protection
Program
Erase
Erase-Suspend Read
(Erase-Suspended Sector)
Erase-Suspend Program
Whenever the system initially begins reading toggle bit status, it must read DQ
determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ
However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
gone high. The system may continue to monitor the toggle bit and DQ
mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status
of the operation. (Refer to Figure 20.)
DW/W pin selects double word (32-bit) mode or word (16-bit) mode for the device. When this pin is driven high,
the device operates in the double word (32-bit) mode. Data is read and programmed at DQ
pin is driven low, the device operates in word (16-bit) mode. In this mode, the DQ
address bit, and DQ
and hence commands are written at DQ
14 for the timing diagram.
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transitions. During power-up, the device automatically resets the internal
state machine to Read mode. Also, with its control register architecture, alteration of memory contents only
occurs after successful completion of the specific multi-bus cycle command sequence.
The device also incorporates several features to prevent inadvertent write cycles resulting from V
and power-down transitions or system noise.
erase suspend sector address will indicate logic “1” at the DQ
Mode
30
to DQ
6
7
/DQ
to DQ
2
16
0
bits are tri-stated. However, the command bus cycle is always an 16-bit operation
on the following read cycle.
Table 11 Toggle Bit Status
31
to DQ
5
DQ
DQ
DQ
70/90
is high (see the section on DQ
0
1
7
7
7
16
and DQ
15
to DQ
0
2
bits are ignored. Refer to Figures 12, 13 and
bit.
Toggle
Toggle
Toggle
DQ
5
1
through successive read cycles, deter-
6
5
). If it is the system should then
7
2
to DQ
to toggle. Reading from non-
31
/A
-1
0
at least twice in a row to
pin becomes the lowest
31
Toggle (Note)
to DQ
1 (Note)
Toggle
DQ
1
0
CC
2
. When this
power-up
5
has not
5