MBM30LV0128 Fujitsu Microelectronics, Inc., MBM30LV0128 Datasheet
MBM30LV0128
Related parts for MBM30LV0128
MBM30LV0128 Summary of contents
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... The I/O pins are utilized for both address and data input/output as well as command inputs. The MBM30LV0128 is an ideal solution for applications requiring mass non-volatile storage such as solid state file storage, digital recording, image file memory for still cameras, and other uses which require high density and non-volatile storage ...
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... MBM30LV0128 FEATURES • 3.3 V-only operating voltage (2 3.6 V) Minimizes system level power requirements • Organization Memory Cell Array : (16 M Data Register : (512 16) • Automatic Program and Erase Page Program : (512 16) Byte Block Erase : (16 K 512) Byte • 528 Byte Page Read Operation Random Access : 10 s (Max ...
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... N.C. 23 N.C. 24 N.C. 24 N.C. 23 N.C. 22 N. ALE 17 CLE 16 N. N. N.C. 5 N.C. 4 N.C. 3 N.C. 2 N.C. 1 MBM30LV0128 TSOP (I) 48 N.C. (Marking Side) 47 N.C. 46 N.C. 45 N.C. 44 I/O7 43 I/O6 42 I/O5 41 I/O4 40 N.C. 39 N. Standard Pinout N.C. 34 N.C. 33 N.C. 32 I/O3 31 I/O2 30 I/O1 29 I/O0 28 N.C. 27 N.C. 26 N.C. 25 N.C. FPT-48P-M19 25 N ...
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... MBM30LV0128 PIN FUNCTIONS PIN Number Pin Name Data Input/Output : The I/O ports are used for transferring command, address, and input/output data I/ into and out of the device. The I/O pins will be high impedance when the outputs are disabled or the device is not selected. ...
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... PIN Number Pin Name 12 V Power Supply CC 13 Ground 10 N.C. Non Connection MBM30LV0128 Pin Functions 5 ...
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... MBM30LV0128 BLOCK DIAGRAM High Voltage Pumps ALE CLE SE State Machine Command Register Address Register Status Register Y-Decoder Data Register & S/A Memory Array Data Register & S/A Y-Decoder I/O Register & Buffer R/B I/O0 to I/O7 ...
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... block address 23 : Page address in block 13 MBM30LV0128 Read and Program operations are executed through Register Register = 1 page size 16) bytes; 32 pages 1024 blocks. I/O5 I/O6 I/ ...
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... MBM30LV0128 DEVICE BUS OPERATIONS Mode Command Input Read Mode Address Input (3 clocks) During Read (Busy) Sequential Read & Data Output Program/ Command Input Erase Address Input ( clocks) Mode Data Input During Program (Busy) During Erase (Busy) Write Protect Stand-by * ...
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... The 01h Command defines starting Address on the 2nd half of the Page. *3: The 50h Command is valid only When SE is low level. Table 4 Command Table 1st Cycle 2nd Cycle 00h * 1 01h * 2 50h * 3 80h 82h 10h 60h D0h FFh 70h 90h MBM30LV0128 Acceptable Command During Busy State 9 ...
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... MBM30LV0128 FUNCTIONAL DESCRIPTION READ MODE There are three distinct commands used for the read operation : 00h, 01h, and 50h. After the command cycle, three address cycles are used to input the starting address. Upon the rising edge of the final WE pulse, there latency in which the 528 byte page is transferred to the data register. The R/B signal may be used to monitor the completion of the data transfer ...
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... Starting Address 50h 0 255 511 527 X (Column Address) Y Figure 3 Read Mode (3) Operation Address Input Data Data 0 255 511 527 0 255 01h 00h, SE Figure 4 Sequential Read MBM30LV0128 Data Output Data 511 527 0 255 511 527 H 50h ...
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... MBM30LV0128 Page Program : 80h, 10h The device is programmed either by the page or partial page. Programming is done by issuing the 80h command followed by three address cycles then serial data input. The 80h command may be preceded by either 00h, 01h or 50h to set the pointer to either the first half page, second half page, or spare area respectively. If the pointer command is not specifically issued, its location is determined by its previous use (see Application Note (2) ) ...
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... Figure 7 Read ID Operation Table 5 Code Table I/O5 I/O4 I/ Table 6 Status Output Table Status 0 Pass; 1 Not Used Not Used Not Used Not Used Not Used Ready/Busy 0 Busy Protected; 1 MBM30LV0128 73h Device Code I/O2 I/O1 I/O0 Code 04h 73h Description Fail Ready Unprotected 13 ...
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... MBM30LV0128 ALE CLE Device ( R/B ALE CLE WE CE (1) CE (N) RE I/O0 to I/O7 Reset When the device is busy during program, erase, or read, it can be reset by entering the command FFh equals 1, the Status Register will be set to C0h reset command is issued while the device is in the reset state, the command will be ignored ...
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... 0.6 CC 0.5 V and on I/O pins are 2.0 V for periods and I/O pins may overshoot to V Symbol Min (Note MBM30LV0128 Rating Unit Max 125 0 0 5 0.5 V. During voltage transitions Value Unit Max ...
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... MBM30LV0128 ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Sequential Read Current Command Address Input Current Data Input Current Program Current Erase Current Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level ...
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... RE Access Time (Status Read) CE Access Time (Status Read) WE High to RE Low ALE Low to RE Low (ID Read) CE Low to RE Low (ID Read) Data Transfer from Memory Cell Array to Register WE High to Busy ALE Low to RE Low (Read Cycle) MBM30LV0128 Value Symbol Unit Min. Max ...
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... MBM30LV0128 (Continued) Parameter RE Last Clock Rising Edge to Busy (in Sequential Read) CE High to Ready (in Case of Interception Read Mode) (Note 2) Device Resetting Time (Read/Program/Erase) Notes : 1. AC Test Conditions : Operating range Input level Input comparison level Output data comparison level Output load Load capacitance (C ...
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... Notes: 1. Refer to Application Note (10) toward the end of this document. 2. This specification is on conditions that ECC systems would be combined. Refer to Application Note (13) toward the end of this document. VALID BLOCKS The MBM30LV0128 occasionally contains unusable blocks. Refer to Application Note (12) toward the end of this document. Parameter Valid Block Number ...
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... MBM30LV0128 TIMING DIAGRAMS CLE t CLS ALS ALE I/O0 to I/O7 Figure 9 Command Input Cycle Timing Diagram t CLE ALE I/O0 to I/O7 Figure 10 Address Input Cycle Timing Diagram 20 t CLH ALH CLS ALS ...
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... CLE CE t ALS ALE WE I/ GND input to D 527 IN V input to D 511 CC IN Figure 11 Data Input Cycle Timing Diagram MBM30LV0128 t CLH ...
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... MBM30LV0128 CE RE I/ R/B Figure 12 Serial Read Cycle Timing Diagram CLE I/O0 to I/O7 R REH REA REA t t RHZ RHZ t CLS t CLS t CLH CSTO WP t WHR 70h Figure 13 Status Read Cycle Timing Diagram ...
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... AR2 ALH REA OUT 255 N 256 to 511 MBM30LV0128 t CEH t CRY ** D OUT D OUT CHZ RHZ D OUT OUT ...
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... MBM30LV0128 CLE t CLH t CLS ALH ALE I/O0 01h to I/O7 Column address R GND input D V input D CC CLE t CLH t CLS ALS t ALH ALE I/O0 50h to I/O7 Column address R GND input D Do not input ALS ...
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... Page Address M Page M Access 256 256 256 t Page Address Page M Page M Access Access 527 511 MBM30LV0128 ** ...
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... MBM30LV0128 CLE CE WE ALE RE I/O0 50h to I/O7 R GND input D Do not input V Note : The CE can be “H or L” after the third address input and during busy state. But, for the sequential read operation, CE must stay “L” after RE toggling for final column address data read and during busy state. ...
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... IN IN 10h 527 of odd page for double page program) IN 511 of odd page for double page program BERASE t WB D0h Erase Start Status Read Command MBM30LV0128 t PROG Status 70h Output Status 70h Output Command V ...
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... MBM30LV0128 CLE t CLS ALH ALE I/O0 90h to I/O7 Figure 23 ID Read Operation Timing Diagram 28 t CLS t t ALH ALS AR1 00h 04h t REAID Address Input Maker Code 73h t REAID Device Code ...
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... Set 01h command is 01h? No Program Sequence Yes Continue to Program? No End MBM30LV0128 setting the start address in 50h within the area in previous use, the 50h command input can be skipped. or (and) 01h area during previous use, the 00h command input can be skipped. or 50h. Yes Start address ...
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... MBM30LV0128 (3) Acceptable commands after serial input command “80h” When the serial input command (80h) is input for program execution, commands other than the program execution command (10h) or reset command (FFh) should not be input Address input R command other than “10h” or “FFh” is input, the program operation is not performed. ...
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... After power-off, each input signal level may be undefined. Use the WP signal as shown in the figure below. 2 DON'T CARE CE, WE, RE CLE, ALE Device R Max 3 Figure 28 Termination for R Operation Figure 29 Power On/Off Sequence MBM30LV0128 by a resistor. CC DON'T CARE ...
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... MBM30LV0128 (8) Setup for WP Signal A Low-level WP signal will force erasing and programming to be reset. To control, use the WP signal as shown below. Program WE DIN WP R/B Program Prohibition WE DIN WP R/B Erase WE DIN WP R/B Erase Prohibition WE DIN WP R 100 ns (Min 100 ns (Min 100 ns (Min.) ...
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... Internal read operation starts when WE in the third cycle goes high. Figure 30 Read Operation when 4 Address Cycles are Input Program operation CLE CE WE ALE I/O0 to I/O7 80h Figure 31 Program Operation when 4 Address Cycles are Input MBM30LV0128 ignored Address input Address input Data input ignored 33 ...
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... MBM30LV0128 (10) Divided programming on same page The device uses a page programming method that allows programming for up to five times on the same page. The procedure for divided programming (programming on a part of one page) is shown below. The first programming Column A Page N Data Pattern 1 The second programming Page N " ...
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... If an error occurs at erasing, like programming, remedies should be executed on a system basis to prevent access to blocks causing the error. Some MBM30LV0128 products have invalid blocks (bad blocks) at shipping. After mounting the device in the system, test whether there are no bad blocks. If there are any bad blocks, they should not be accessed ...
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... MBM30LV0128 (14) CE “don’t care” timing for read and program operation CE can be “don’t-care” (“H” or “L”) state during read and program operation as follows. <Read Operation> I/ Command I/O7 R/B (55 ns (Max.)) t CEA CE t REA RE I/O0 to I/O7 <Program Operation> ...
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... BAD BLOCK TEST FLOW Block No. Block No. 1 Yes Figure 36 Bad Block Test Flow MBM30LV0128 Test Start Block No. 0 Page 0 & Set as a bad block Blank Check "All FFh?" Yes B No. 1023 No Test End 37 ...
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... Fujitsu standard products are available in several packages. The order number is formed by a combination of : MBM30LV0128 -PFTN DEVICE NUMBER/DESCRIPTION MBM30LV0128 128 Mega-bit ( 3.6 V Read, Write, and Erase Valid Combinations MBM30LV0128 38 PACKAGE TYPE PFTN 48-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR 48-Pin Thin Small Outline Package ...
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... LEAD No. 1 INDEX 24 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) 0.10(.004) 19.00±0.20 (.748±.008) 2000 FUJITSU LIMITED F48029S-2C-3 C MBM30LV0128 * : Resin protrusion. (Each side : 0.15 (.006) Max) 48 Details of "A" part 0.15(.006) "A" 0.15(.006) 0.25(.010 12.00±0.20 (.472±.008) 11.50REF (.460) ...
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... MBM30LV0128 (Continued) 48-pin plastic TSOP (II) (FPT-48P-M20) LEAD No. 1 INDEX 24 19.00±0.20 (.748±.008) 0.10(.004) * 18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) 2000 FUJITSU LIMITED F48030S-2C Resin protrusion. (Each side : 0.15 (.006) Max) 48 Details of "A" part 0.15(.006) MAX "A" ...
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... MBM30LV0128 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. ...