MBM30LV0128 Fujitsu Microelectronics, Inc., MBM30LV0128 Datasheet - Page 34

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MBM30LV0128

Manufacturer Part Number
MBM30LV0128
Description
Flash Memory 128 M 16 M X 8 Bit Nand-type
Manufacturer
Fujitsu Microelectronics, Inc.
Datasheet
34
MBM30LV0128
(10) Divided programming on same page
(11) Notification for RE Signal
The device uses a page programming method that allows programming for up to five times on the same page.
The procedure for divided programming (programming on a part of one page) is shown below.
When the device is in the read mode, the RE signal causes the internal column address counter to increment
in synchronization with the RE clock. If the 00h, 01h, or 50h command is input to the device in the read mode,
the internal column address counter will count up even after the RE signal is input prior to address input. At this
mode, And at input of the RE signal beyond the last column address, the device will start reading (Memory
register) even without address input and may output the Busy signal (Sequential Read is started) .
In this way, once the device enters the read mode, unintentional reading may be started after the RE signal is
input prior to addressing; therefore, the RE signal should be input after the address input.
I/O0 to I/O7
The first programming
The second programming
The third programming
Result
WE
RE
R/B
Page N
Page N
Page N
Page N
00h/01h
/50h
Column A
Column A
Data Pattern 1
Data Pattern 1
Figure 32 Divided Program in the Same Page
"No Input" or "1"
Figure 33 RE Input Before Address
Column B
Column B
"No Input" or "1"
"1"
Column C
Column C
Data Pattern 2
Data Pattern 2
"No Input" or "1"
Column D
Column D
"1"
Column E
Column E
Address input
"No Input" or "1"
Data Pattern 3
Data Pattern 3
Column F
Column F
"No Input"
or "1"
"1"

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