MBM30LV0128 Fujitsu Microelectronics, Inc., MBM30LV0128 Datasheet - Page 4

• Manufacturer Part Number: MBM30LV0128
• Description: Flash Memory 128 M 16 M X 8 Bit Nand-type
• Manufacturer: Fujitsu Microelectronics, Inc.

4
MBM30LV0128
PIN Number
PIN FUNCTIONS
29 to 32
41 to 44
16
17
18
19
37
9
8
6
7
I/O0 to I/O7
Pin Name
V
CLE
ALE
WE
WP
R/B
CE
RE
SE
CC
q
Data Input/Output :
The I/O ports are used for transferring command, address, and input/output data
into and out of the device. The I/O pins will be high impedance when the outputs
are disabled or the device is not selected.
Command Latch Enable :
The CLE signal enables the acquisition of the mode command into the internal
command register. When CLE “H”, command is latched into the command reg-
ister from the I/O port upon the rising edge of the WE signal.
Address Latch Enable :
The ALE signal enables the acquisition of either addresses or data into the inter-
nal address/data register. The rising edge of WE will latch in addresses when
ALE is high and data when ALE is low.
Chip Enable :
The CE signal is used to select the device. When CE is high, the device enters
a low power standby mode. If CE transitions are high during a read operation,
the standby mode will be entered. However, the CE signal is ignored if the device
is in a busy state (R/B
Read Enable :
The RE signal controls the serial data output. The falling edge of RE drives the
data onto the I/O bus and increments the column address counter by one.
Write Enable :
The WE signal controls write from the I/O port. Data, address, and commands on
the I/O port are latched upon the rising edge of the WE pulse.
Write Protect :
The WP signal protects the device against accidental erasure or programming
during power up/down by disabling the internal high voltage generators. WP
should be kept low when the device powers up until Vcc is above 2.5 V. During
power down, WP should be low when Vcc falls below 2.5 V.
Spare Area Enable :
The SE input enables the spare area during sequential data input, page program,
and Read 1.
Ready Busy Output :
The R/B output signal is used to indicate the operating status of the device. Dur-
ing program, erase, or read, R/B is low and will return high upon the completion
of the operation. The output buffer for this signal is an open drain.
Output Buffer Power Supply :
The V
electrically isolated from V
CC
q input supplies the power to the I/O interface logic. This power line is
“L”) during a program or erase operation.
CC
for the purpose of supporting 5 V tolerant I/O.
Pin Functions
(Continued)