MSC8144 Freescale Semiconductor, MSC8144 Datasheet - Page 54

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MSC8144

Manufacturer Part Number
MSC8144
Description
Quad Core Digital Signal Processor
Manufacturer
Freescale Semiconductor
Datasheet

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2.7.9
Figure 24 shows the timer input AC timing
2.7.10
This section describes the AC electrical characteristics for the Ethernet interface.
There are programmable delay units (PDU) that should be programmed differently for each Interface to meet timing. There is
a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8144 Reference
Manual.
2.7.10.1
54
TIMERx frequency
TIMERx Input high phase
TIMERx Output low phase
ETHMDC clock pulse width high
ETHMDC to ETHMDIO delay
ETHMDIO to ETHMDC rising edge set-up time
ETHMDC rising edge to ETHMDIO hold time
ETHMDC rise time.
ETHMDC fall time.
Notes:
1.
2.
TIMERx (Input)
Timer Timing
Ethernet Timing
Typical ETHMDC frequency (f
example, for a source clock of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz. For a
375 MHz clock, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz.
The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of
333 MHz, the delay is 58 ns.
Management Interface Timing
2
Table 42. Ethernet Controller Management Interface Timing
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1
Characteristics
Characteristics
MDC
) is 2.5 MHz with a 400 ns period (t
Figure 24. Timer Timing
Table 41. Timer Timing
T
TMCH
T
TMREFCLK
T
TMCL
MDC
t
t
t
Symbol
MDKHDX
MDDVKH
MDDXKH
t
t
t
). The value depends on the source clock. For
MDCH
MDCR
MDHF
T
Symbol
TMREFCLK
T
T
TMCH
TMCL
Min
32
10
5
0
Freescale Semiconductor
Max
10.0
Min
70
10
10
4.0
4.0
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

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