MSC8144 Freescale Semiconductor, MSC8144 Datasheet - Page 66

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MSC8144

Manufacturer Part Number
MSC8144
Description
Quad Core Digital Signal Processor
Manufacturer
Freescale Semiconductor
Datasheet

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Hardware Design Considerations
3.1.2
Section 2.7.1 describes the start-up timing.
3.2
3.2.1
Each PLL supply must have an external RC filter for the V
low ESL (<0.5 nH) and low ESR capacitors. All three PLLs can connect to a single supply voltage source (such as a voltage
regulator) as long as the external RC filter is applied to each PLL separately (see Figure 46). For optimal noise filtering, place
the circuit as close as possible to its V
3.2.2
TBD
3.3
Note:
First, select the pin multiplexing mode to allocate the required I/O signals. Then use the guidelines presented in the following
subsections for board design and connections. The following conventions are used in describing the connectivity requirements:
66
1.
Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal
connections in this discussion.
GND indicates using a 10 kΩ pull-down resistor (recommended) or a direct connection to the ground plane. Direct
connections to the ground plane may yield DC current up to 50mA through the I/O supply that adds to overall power
consumption.
Voltage Regulator
Power Supply Design Considerations
Connectivity Guidelines
Start-Up Timing
PLL Supplies
Other Supplies
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1
2.2 μF
2.2 μF
2.2 μF
DDPLL
inputs. These traces should be short and direct.
Figure 46. PLL Supplies
10 Ω
10 Ω
10 Ω
2.2 μF
2.2 μF
2.2 μF
DDPLL
input. The filter is a 10 Ω resistor in series with two 2.2 μF,
V
V
V
DDPLL0
DDPLL0
DDPLL0
MSC8144
Freescale Semiconductor

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