MCD212 Motorola, MCD212 Datasheet - Page 62

• Manufacturer Part Number: MCD212
• Description: Video Decoder and System Controller(with JTAG)
• Manufacturer: Motorola

The region control registers are examined on their specified horizontal position sequentially. Depend-
ing on the mode, this sequence ranges from 0 to 7 or from 0 to 3 and from 4 to 7. When a match
between the specified horizontal position and the actual horizontal pixel count is found, the corre-
sponding command is executed. This command can set/reset the corresponding or specified region
flag, change one of the two weight factors, or end the region control for the line (no further registers
are examined). So for all registers to be noticed, the position sequence stored in the region control
registers has to be ascending (see Figures 8–3 and 8–4). The horizontal position is specified with
respect to the double rate clock (maximally 768 pixels per line). The region flags are automatically
reset before the start of each line.
8.4
Transparency of planes can be obtained by:
The image planes (A/B) and the cursor can be made transparent by disabling them.
Parts of both image planes can be made transparent depending on the state of one of the two region
flags.
For both image planes a color key is available for CLUT decoded images. The state of the color key
is determined on a pixel basis. Every CLUT decoded pixel is compared to an in RGB666 specified
color; the so–called transparent color. If all bits match or if the corresponding mask bit is true, the color
key is true.
A transparency bit is available from every direct RGB555 coded pixel.
8.5
The four planes must be combined into one image. This is achieved by overlay and mixing. Overlay
means that only one plane at a time is shown. This is done by giving the planes an order and by using
transparency, a plane can only be seen if it is not transparent and all higher order planes are transpar-
ent. The order is from high to low cursor, plane A/plane B, backdrop. The order of A and B can be
selected A in front of B or B in front of A (see Figure 8–5).
It is also possible to overlay external video as an alternative for backdrop. This is done by using an
external switch operated by the VDSC pin VSD or VSA. The VSD signal is synchronous to the digital
output, whereas VSA is delayed one CLK2 clock cycle to counteract for a delay caused by a clocked
DAC. VSD and VSA are active if enabled by the EV–bit of the “image coding method register” and
when the backdrop is shown.
MOTOROLA
Disabling
Regions
Color Key
Transparency Bit
TRANSPARENCY
OVERLAY AND MIXING
Figure 8–5. Plane Order
CURSOR PLANE
GRAPHICS PLANE B
GRAPHICS PLANE A
BACKGROUND/EXTERNAL VIDEO
MCD212
8–3