MCD212 Motorola, MCD212 Datasheet - Page 65

• Manufacturer Part Number: MCD212
• Description: Video Decoder and System Controller(with JTAG)
• Manufacturer: Motorola

9–2
9.1
9.1.1
These registers control the system related functions of the VDSC. They are reset to 0 during the initial-
ization sequence. This is the default configuration.
CSR1W (write, 4FFFF0)
CSR1W
CSR2W
CSR1R
CSR2R
Name
DCR1
DCR2
DDR1
DDR2
VSR1
VSR2
DCP1
DCP2
DI1
DD1 – DD2
TD
DD
DI1
15
REGISTER MAP
Control Registers CSR1W and CSR2W
DI1
DI2
DE
14
—
15
x
x
x
x
x
*
*
*
*
13
—
CF
14
x
x
x
x
x
x
x
*
*
*
*
(Disable Interrupts) When set to 1, disables the propagation to the INT pin
for the IT1 bit (see STATUS register). This bit does not disable the IT1 bit.
(DTACK delay) Active when DD = 1. These two bits permit four different
delays for the DTACK generation when the CPU accesses the system ROM.
(Type of DRAM) to be 0 for 256K x 4 and 256K x 16 devices and 1 for
1M x 4 devices.
DTACK Delay for the ROM. See DD1 – DD2.
Table 9–3. Control Register 1 — Write, 4FFFF0
12
—
FD
13
x
x
x
x
x
x
x
*
*
*
*
11
—
SM
12
x
x
x
x
x
x
x
*
*
*
*
DD
Table 9–2. Register Bitmap
10
—
0
1
1
1
1
CM1
CM2
MF1
MF1
Table 9–4. DTACK Delay
10
x
x
x
x
*
*
*
*
DD1
9
DD1
DD1
MF2
MF2
x
0
0
1
1
9
0
0
x
x
x
*
*
*
*
DD2
MCD212
8
DD2
FT1
FT1
IC1
IC2
8
x
x
x
*
*
*
*
DD2
x
0
1
0
1
—
7
DC1
DC2
FT2
FT2
DA
7
x
x
x
*
*
*
*
CLK Cycles
—
6
11
9
3
5
7
6
x
x
x
x
x
x
x
x
*
*
*
*
10
12
TD
4
6
8
5
PA
TD
5
x
x
x
x
x
x
*
*
*
*
—
4
4
x
x
x
x
*
*
*
*
*
*
*
*
DD
3
DD
3
x
x
x
*
*
*
*
*
*
*
*
—
2
IT1
2
x
x
x
*
*
*
*
*
*
*
*
ST
1
IT2
ST
1
x
x
x
x
*
*
*
*
*
*
BE
0
MOTOROLA
BE
BE
0
x
x
*
*
*
*
*
*
x
x