MCD212 Motorola, MCD212 Datasheet - Page 68
![no-image](/images/manufacturer_photos/0/4/459/motorola_sml.jpg)
MCD212
Manufacturer Part Number
MCD212
Description
Video Decoder and System Controller(with JTAG)
Manufacturer
Motorola
Datasheet
1.MCD212.pdf
(87 pages)
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DCR2 (write, 4FFFE2)
MOTOROLA
CM1
IC1 – DC1
A21 – A16
CM2
IC2 – DC2
A21 – A16
15
—
14
—
Table 9–13. Display Command Register DCR2 — Write, 4FFFE2
13
—
(Color Mode of channel 1) This bit controls the pixel output mode.
(ICA1 – DCA1) These two bits enable the ICA1 and DCA1 mechanisms.
Most significant bits of the video start address, acting in conjunction with the
VSR.
(Color Mode of channel 2) This bit controls the pixel output mode.
(ICA2 – DCA2) These two bits enable the ICA2 and DCA2 mechanisms.
Most significant bits of the video start address, acting in conjunction with the
VSR.
12
—
CM2
11
Table 9–14. Channel 2 Color Mode
Table 9–11. Channel 1 Color Mode
CM1
CM2
Table 9–12. ICA1/DCA1 Enable
Table 9–15. ICA1/DCA1 Enable
1
0
1
IC1
IC2
10
0
1
1
0
1
1
0
Table 9–10. Scan Mode
SM
IC2
0
1
Bits/Pixel
Bits/Pixel
9
DC1
DC2
x
0
1
x
0
1
4
8
4
DC2
MCD212
8
Non–interlace
Scan Mode
Interlace
ICA1
ICA2
Yes
Yes
Yes
Yes
No
No
—
7
Pixel Frequency
Pixel Frequency
—
6
CLK/2
CLK/4
CLK/2
DCA1
DCA2
Yes
Yes
No
No
No
No
A21
5
A20
4
A19
3
A18
2
A17
1
A16
0
9–5
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