MB81F641642D Fujitsu Microelectronics, MB81F641642D Datasheet
MB81F641642D
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MB81F641642D Summary of contents
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... RAM (DRAM) which requires many control signal timing constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM. The MB81F641642D is ideally suited for workstations, personal computers, laser printers, high resolution graphic adapters/accelerators and other applications where an extremely large memory and bandwidth are required and where a simple interface is needed. PRODUCT LINE & ...
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... MB81F641642D-75/-102/-102L PACKAGE Package and Ordering Information – 54-pin plastic (400 mil) TSOP-II, order as MB81F641642D- MB81F641642D- LFN (Low power version) 2 Preliminary (AE4.1E) 54-pin plastic TSOP(II) Marking side (FPT-54P-M02) (Normal Bend) FN (Standard version) or ...
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... MB81F641642D-75/-102/-102L PIN ASSIGNMENTS AND DESCRIPTIONS Pin Number 14, 27, 43 10, 11, 13, 42, 44, 45, 47, 48, 50, 51 12, 28, 41, 46, 52 22, 23, 24, 25, 26, 29, 30, 31, 32, 33 These pins are connected internally in the chip. ...
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... ADDRESS BUFFER/ REGISTER A (BA1 (BA0) 13 DQMU I/O DATA BUFFER/ REGISTER Fig. 1 – MB81F641642D BLOCK DIAGRAM To each block CONTROL SIGNAL LATCH MODE REGISTER COLUMN ADDRESS COUNTER Preliminary (AE4.1E) BANK-3 BANK-2 BANK-1 BANK-0 RAS CAS WE DRAM CORE (4,096 256 ...
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... MB81F641642D-75/-102/-102L FUNCTIONAL TRUTH TABLE Note *1 COMMAND TRUTH TABLE Function Notes Symbol Device Deselect *5 No Operation *5 Burst Stop Read *6 READ Read with Auto-precharge *6 READA Write *6 Write with Auto-precharge *6 WRITA Bank Active *7 Precharge Single Bank Precharge All Banks Mode Register Set *8, 9 Notes: *1 ...
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... MB81F641642D-75/-102/-102L DQM TRUTH TABLE Function Data Write/Output Enable for Lower Byte Data Write/Output Enable for Upper Byte Data Mask/Output Disable for Lower Byte Data Mask/Output Disable for Upper Byte CKE TRUTH TABLE Current Function State Bank Active Clock Suspend Mode Entry ...
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... MB81F641642D-75/-102/-102L OPERATION COMMAND TABLE (Applicable to single bank) Note *1 Current CS RAS CAS WE State Idle Bank Active ...
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... MB81F641642D-75/-102/-102L Current CS RAS CAS WE State Read Write Preliminary (AE4.1E) Addr Command X X DESL ...
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... MB81F641642D-75/-102/-102L Current CS RAS CAS WE State Read with Auto- precharge Write with Auto- precharge Addr ...
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... MB81F641642D-75/-102/-102L Current CS RAS CAS WE State Precharging Bank Activating Preliminary (AE4.1E) Addr Command X X DESL ...
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... MB81F641642D-75/-102/-102L (Continued) Current CS RAS CAS State Refreshing Mode Register Setting ABBREVIATIONS Row Address BA = Bank Address CA = Column Address AP = Auto Precharge Notes: *1. All entries in OPERATION COMMAND TABLE assume the CKE was High during the proceeding clock cycle and the current clock cycle. Illegal means don’ ...
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... MB81F641642D-75/-102/-102L COMMAND TRUTH TABLE FOR CKE Note *1 Current CKE CKE CS State n-1 n Self refresh Self refresh Recovery RAS CAS WE Addr ...
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... MB81F641642D-75/-102/-102L Current CKE CKE CS State n-1 n Power Down All Banks Idle RAS CAS ...
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... MB81F641642D-75/-102/-102L (Continued) Current CKE CKE CS State n-1 n Bank Active H H Bank Activating Read/Write H L Read with Auto- precharge/ Write with Auto precharge Clock H X Suspend Any State L X Other Than Listed H H Above H L Notes: *1. All entries in COMMAND TRUTH TABLE FOR CKE are specified at CKE(n) state and CKE input from CKE(n-1) to CKE(n) state must satisfy corresponding set up and hold time for CKE ...
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... MB81F641642D-75/-102/-102L FUNCTIONAL DESCRIPTION SDRAM BASIC FUNCTION Three major differences between this SDRAM and conventional DRAMs are: synchronized operation, burst mode, and mode register. The synchronized operation is the fundamental difference. An SDRAM uses a clock input for the synchronization, where the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each operation of DRAM is determined by their timing phase differences while each operation of SDRAM is determined by commands and all operations are referenced to a positive clock edge ...
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... MB81F641642D-75/-102/-102L DATA INPUTS AND OUTPUTS (DQ Input data is latched and written into the memory at the clock following the write command input. Data output is obtained by the following conditions followed by a read command input from the bank active command when t RAC t ; from the read command when t ...
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... MB81F641642D-75/-102/-102L (Continued) When the full burst operation is executed at single write mode, Auto-precharge command is valid only at write operation. The burst type can be selected either sequential or interleave mode. But only the sequential mode is usable to the full column burst. The sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address (= 0) ...
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... MB81F641642D-75/-102/-102L PRECHARGE AND PRECHARGE OPTION (PRE, PALL) SDRAM memory core is the same as conventional DRAMs’, requiring precharge and refresh operations. Precharge rewrites the bit line and to reset the internal Row address line and is executed by the Precharge command (PRE). With the Precharge command, SDRAM will automatically be in standby state after precharge time (t ...
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... MB81F641642D-75/-102/-102L POWER-UP INITIALIZATION The SDRAM internal condition after power-up will be undefined required to follow the following Power On Sequence to execute read or write operation. 1. Apply power and start clock. Attempt to maintain either NOP or DESL command at the input. 2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 s. ...
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... MB81F641642D-75/-102/-102L Fig. 2 – BASIC TIMING FOR CONVENTIONAL DRAM VS SYNCHRONOUS DRAM <SDRAM> Active CLK H CKE RAS CAS WE Address <Conventional DRAM> Row Address Select RAS CAS DQ 20 Read/Write Read L : Write Column Address Select Preliminary (AE4 ...
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... MB81F641642D-75/-102/-102L Fig. 3 – STATE DIAGRAM (Simplified for Single BANK Operation State Diagram) MRS MODE REGISTER SET CKE\(CSUS) BANK CKE ACTIVE SUSPEND BST WRIT CKE\(CSUS) WRITE WRITE SUSPEND CKE WRITA CKE\(CSUS) WRITE WITH WRITE AUTO SUSPEND CKE\ ...
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... MB81F641642D-75/-102/-102L BANK OPERATION COMMAND TABLE MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION Second command (same bank) First command MRS t t RSC RSC ACTV READ *1 *2 READA BL+ BL WRIT *2 WRITA BL-1 BL DAL DAL *2 *3 PRE ...
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... MB81F641642D-75/-102/-102L MULTI BANK OPERATIVE COMMAND TABLE MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION Second command (other bank) First command MRS t t RSC RSC *2 ACTV t RRD *2 *4 READ READA BL WRIT WRITA ...
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... MB81F641642D-75/-102/-102L MODE REGISTER TABLE MODE REGISTER SET Op code Burst Read & Burst Write 1 Burst Read & Single Write * Notes: *1. When A * and Full Column are not applicable to the interleave mode. ...
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... MB81F641642D-75/-102/-102L ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Voltage of V Supply Relative Voltage at Any Pin Relative Short Circuit Output Current Power Dissipation Storage Temperature WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ...
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... Output Low Voltage Input Leakage Current (Any Input) Output Leakage Current MB81F641642D-75 MB81F641642D-102 Operating Current (Average Power Supply Current) Reference Value @66MHz(CL=2) MB81F641642D-75 MB81F641642D Precharge Standby Current MB81F641642D-75 (Power Supply Current) MB81F641642D-102 Reference Value @66MHz(CL=2) 26 Preliminary (AE4.1E) Symbol Condition –2 mA OH(DC) ...
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... Current (Power Supply MB81F641642D-102 Current) Reference Value @66MHz(CL=2) MB81F641642D-75 Burst mode Current MB81F641642D-102 (Average Power Supply Current) Reference Value @66MHz(CL=2) MB81F641642D-75 Refresh Current #1 MB81F641642D-102 (Average Power Supply Current) Reference Value @66MHz(CL=2) MB81F641642D-75 Refresh Current #2 (Average Power MB81F641642D- Supply Current) 102L Notes: *1. All voltage are referenced ...
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... Output in High-Z *5 Output Hold Time *5 Time between Auto-Refresh command interval *4 Time between Refresh Transition Time CKE Setup Time for Power Down *5 Exit Time 28 Preliminary (AE4.1E) MB81F641642D MB81F641642D -75 -102/-102L Symbol Min. Max. Min CK2 — t 7.5 10 CK3 t 2.5 — ...
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... DPL 1 cyc t — — DAL2 + cyc t — — DAL3 + — RSC Note *10 (Round off a whole number) Preliminary (AE4.1E) *4 Reference MB81F641642D Value -102/-102L @66MHz(CL=2) Min. Max. Min. Max. 70 — 80 — 20 — 30 — 50 110000 50 110000 20 — 30 — 10 — ...
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... All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). 30 Preliminary (AE4.1E) MB81F641642D MB81F641642D Symbol - CKE ...
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... MB81F641642D-75/-102/-102L Fig. 4 – OUTPUT LOAD CIRCUIT Output Note: By adding appropriate correlation factors to the test conditions coupled to the Output Load Circuit are within specifications LVTTL and t measured when the output AC OH Preliminary (AE4.1E) 31 ...
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... MB81F641642D-75/-102/-102L Fig. 5 – TIMING DIAGRAM, SETUP, HOLD AND DELAY TIME 2.4 V CLK 0.4 V Input (Control, Addr. & Data) 2.4 V Output 0.4 V Note: Reference level of input signal is 1.4 V for LVTTL. Access time is measured at 1.4 V for LVTTL. Fig. 6 – TIMING DIAGRAM, DELAY TIME FOR POWER DOWN EXIT CLK Don’ ...
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... MB81F641642D-75/-102/-102L Fig. 7 – TIMING DIAGRAM, PULSE WIDTH CLK Input (Control) COMMAND Note: These parameters are a limit value of the rising edge of the clock from one command input to next input. t latency value from the rising edge of CKE. Measurement reference voltage is 1.4 V. ...
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... MB81F641642D-75/-102/-102L TIMING DIAGRAMS TIMING DIAGRAM – CLOCK ENABLE - READ AND WRITE SUSPEND (@ CLK CKE CLK (Internal) DQ (Read) DQ (Write) Notes: *1. The latency of CKE (l *2. During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output data remain the same data. ...
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... MB81F641642D-75/-102/-102L TIMING DIAGRAM – COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY CLK RAS t RCD CAS ROW Address ADDRESS Note: CAS to CAS delay can be one or more clock period. TIMING DIAGRAM – DIFFERENT BANK ADDRESS INPUT DELAY CLK t RRD RAS t RCD CAS ...
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... MB81F641642D-75/-102/-102L TIMING DIAGRAM – DQMU, DQML - INPUT MASK AND OUTPUT DISABLE (@ CLK DQML, DQMU (@ Read Read) DQML, DQMU (@ Write Write) TIMING DIAGRAM – PRECHARGE TIMING (APPLIED TO THE SAME BANK) CLK Command Note: PRECHARGE means ‘PRE’ or ‘PALL’. ...
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... MB81F641642D-75/-102/-102L TIMING DIAGRAM – READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CLK Command PRECHARGE DQ Command DQ Command DQ Command DQ Note: In case the clocks. ROH In case the clocks. ROH PRECHARGE means ‘PRE’ or ‘PALL’ clocks) ROH Hi-Z Q1 PRECHARGE ...
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... MB81F641642D-75/-102/-102L TIMING DIAGRAM – READ INTERRUPTED BY BURST STOP (EXAMPLE @ BL = Full Column) CLK Command ( n–2 Command ( n-2 TIMING DIAGRAM – WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ CLK Command DQ 38 Preliminary (AE4.1E) BST l (2 clocks) BSH n–1 ...
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... MB81F641642D-75/-102/-102L TIMING DIAGRAM – WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CLK Command DQ D n-1 Note: The precharge command (PRE) should only be issued after the t PRECHARGE means ‘PRE’ or ‘PALL’. TIMING DIAGRAM – READ INTERRUPTED BY WRITE (EXAMPLE @ CLK Command ...
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... MB81F641642D-75/-102/-102L TIMING DIAGRAM – WRITE TO READ TIMING (EXAMPLE @ CLK Command DQM (DQML, DQMU) DQ Note: Read command should be issued after t 40 Preliminary (AE4.1E) t (min) WR WRIT READ (CL- Masked by READ of final data input is satisfied (max ...
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... MB81F641642D-75/-102/-102L TIMING DIAGRAM – READ WITH AUTO-PRECHARGE (EXAPLE @ Applied to same bank) CLK Command ACTV DQM (DQML, DQMU) DQ Notes: *1. Precharge at Read with Auto-precharge command (READA) is started from number of clocks that is the same as Burst Length (BL) after the READA command is asserted. ...
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... MB81F641642D-75/-102/-102L TIMING DIAGRAM – AUTO-REFRESH TIMING CLK *1 Command REF * BA) DON’T CARE 12 13 Notes: *1. All banks should be precharged prior to the first Auto-refresh command (REF). *2. Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter. ...
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... MB81F641642D-75/-102/-102L TIMING DIAGRAM – MODE REGISTER SET TIMING CLK Command MRS Address MODE Note: The Mode Register Set command (MRS) should only be asserted after all banks have been precharged. t (min) RSC NOP or DESL ACTV ROW ADRESS Preliminary (AE4.1E) 43 ...
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... MB81F641642D-75/-102/-102L PACKAGE DIMENSION 54-pin plasticTSOP(II) (FPT-54P-M02) 54 "A" INDEX LEAD No +0.08 0.32 –0.07 0.16(.006) +.003 .013 –.003 0.80(.0315) 0.10(.004) TYP 20.80(.819)REF 1997 FUJITSU LIMITED F54003S-1C 22.22±0.10 1.15±0.05 (.875±.004) (.045±.002) (Mounting height) M 0.05(.002)MIN (STAND OFF) Preliminary (AE4 ...
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... MB81F641642D-75/-102/-102L MEMO Preliminary (AE4.1E) 45 ...
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... MB81F641642D-75/-102/-102L MEMO 46 Preliminary (AE4.1E) ...
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... MB81F641642D-75/-102/-102L MEMO Preliminary (AE4.1E) 47 ...
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... MB81F641642D-75/-102/-102L FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. ...