MB81F641642D Fujitsu Microelectronics, MB81F641642D Datasheet - Page 22

• Manufacturer Part Number: MB81F641642D
• Description: 4 x 1M x 16-Bit SDRAM
• Manufacturer: Fujitsu Microelectronics

22
MB81F641642D-75/-102/-102L
MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION
Notes: *1. If t
First
command
BANK OPERATION COMMAND TABLE
READA
WRITA
SELFX
PALL
READ
ACTV
WRIT
MRS
command
PRE
REF
*2. Assume all banks are in Idle state.
*3. Assume output is in High-Z state.
*4. Assume t
*5. Assume no I/O conflict.
*6. Assume after the last data have been appeared on DQ.
*7. If t
Second
(same
bank)
Illegal Command
RP
RP
(min)
(min)
+ t
BL-1
BL+
t
t
t
t
t
t
RSC
RP
RP
RP
RC
RC
DAL
RAS
*1
*2
*2
*2
*3
*3
CL
(CL-1)
(min) is satisfied.
+ t
BL-1
BL+
t
t
t
t
t
t
RSC
RP
RP
RP
RC
RC
DAL
t
CK
, minimum latency is a sum of (BL + CL)
t
CK
, minimum latency is a sum of (BL + CL-1)
t
RCD
t
1
WR
t
RCD
t
1
*4
WR
t
RCD
1
1
*5
t
RCD
1
*4
1
*5
Preliminary (AE4.1E)
+ t
BL-1
BL+
t
t
t
t
t
t
DPL
RSC
RAS
1
RP
1
1
RC
RC
DAL
*4
*4
*4
*4
t
CK
.
+ t
BL-1
BL+
t
t
t
t
t
t
t
DPL
RSC
RAS
CK
1
RP
1
1
RC
RC
DAL
.
*4
*4
*4
*4
*4
+ t
BL-1
BL+
t
t
t
t
t
t
RSC
RP
RP
RP
RC
RC
DAL
*2
*2
*2
+ t
BL-1
BL+
t
t
t
t
t
t
RSC
RP
RP
RP
RC
RC
DAL
*2
*7
*2
*2
*6
*6
t
t
t
RSC
1
1
1
1
1
RC
RC