MB81F641642D Fujitsu Microelectronics, MB81F641642D Datasheet - Page 11

• Manufacturer Part Number: MB81F641642D
• Description: 4 x 1M x 16-Bit SDRAM
• Manufacturer: Fujitsu Microelectronics

(Continued)
ABBREVIATIONS:
Notes: *1. All entries in OPERATION COMMAND TABLE assume the CKE was High during the proceeding clock
Refreshing
Mode
Register
Setting
Current
State
RA = Row Address
CA = Column Address
*2. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state
*3. Illegal if any bank is not idle.
*4. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
*5. NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP).
*6. SELF command should only be issued after the last read data have been appeared on DQ.
*7. MRS command should only be issued on condition that all DQ are in Hi-Z.
cycle and the current clock cycle.
Illegal means don’t used command. If used, power up sequence be asserted after power shut down.
of that bank.
Refer to TIMING DIAGRAM -11 & -12.
CS
H
H
L
L
L
L
L
L
L
L
RAS CAS
MB81F641642D-75/-102/-102L
X
H
H
H
H
H
X
L
L
L
BA = Bank Address
AP = Auto Precharge
X
H
H
X
H
H
X
L
L
L
WE
X
X
X
X
X
X
H
X
X
L
Addr
X
X
X
X
X
X
X
X
X
X
READ/READA/
READ/READA/
WRIT/WRITA
WRIT/WRITA
ACTV/PRE/
REF/SELF/
PALL/REF/
SELF/MRS
Command
PRE/PALL
NOP/BST
ACTV/
DESL
DESL
MRS
NOP
BST
NOP (Idle after t
NOP (Idle after t
Illegal
Illegal
Illegal
NOP (Idle after t
NOP (Idle after t
Illegal
Illegal
Illegal
Function
Preliminary (AE4.1E)
RC
RC
RSC
RSC
)
)
)
)
Notes
11