MB81F641642D Fujitsu Microelectronics, MB81F641642D Datasheet - Page 39

• Manufacturer Part Number: MB81F641642D
• Description: 4 x 1M x 16-Bit SDRAM
• Manufacturer: Fujitsu Microelectronics

CLK
Command
DQ
Note: The precharge command (PRE) should only be issued after the t
CLK
Command
DQM
(DQML, DQMU)
DQ
Notes: *1. First DQM makes high-impedance state High-Z between last output and first input data.
TIMING DIAGRAM – 10 : WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 3)
TIMING DIAGRAM – 11 : READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 3, BL = 4)
PRECHARGE means ‘PRE’ or ‘PALL’.
*2. Second DQM makes internal output data mask to avoid bus contention.
*3. Third DQM in illustrated above also makes internal output data mask. If burst read ends (final data output) at or after the
second clock of burst write, this third DQM is required to avoid internal bus contention.
READ
MB81F641642D-75/-102/-102L
D
n-1
LAST D
*1
n
t
DPL
(min)
PRECHARGE
I
DQZ
by Precharge
MASKED
(2 clocks)
Q
*2
DPL
1
of final data input is satisfied.
I
OWD
t
Masked
RP
(2 clocks)
(min)
*3
ACTV
WRIT
D
1
I
Preliminary (AE4.1E)
DWD
(same clock)
D
2
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