S3033 AMCC (Applied Micro Circuits Corp), S3033 Datasheet

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S3033

Manufacturer Part Number
S3033
Description
Bicmos Lvpecl Clock Generator Sonet/sdh/atm Oc-12 Transmitter And Sonet/sdh/atm Oc-3/oc-12 Transceiver
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet
FEATURES
APPLICATIONS
Figure 1. System Block Diagram
DEVICE
SPECIFICATION
April 12, 2000 / Revision D
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
BiCMOS LVPECL CLOCK GENERATOR
• Complies with Bellcore and ITU-T
• On-chip high-frequency PLLs for clock
• Supports 155.52 Mbit/s (OC-3) and 622.08
• Selectable reference frequencies of 19.44,
• Interface to both LVPECL and TTL logic
• Redundant receiver inputs
• Redundant transmitter outputs
• 8-bit TTL data path
• Compact 14 mm 80 PQFP package
• Diagnostic loopback mode
• Lock detect
• Low jitter LVPECL interface
• Single 3.3 V supply
• SONET/SDH-based transmission systems
• SONET/SDH modules
• SONET/SDH test equipment
• ATM over SONET/SDH
• Section repeaters
• Add Drop Multiplexers (ADM)
• Broad-band cross-connects
• Fiber optic terminator
• Fiber optic test equipment
• ATM switch backbones requiring redundancy
specifications
generation and clock recovery
Mbit/s (OC-12)
38.88, 51.84 or 77.76 MHz
Processor
Interface
Network
8
8
SONET/SDH
Transceiver
S3035
OTX
OTX
ORX
ORX
GENERAL DESCRIPTION
The S3035 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET
OC-12 (622.08 Mbit/s) and OC-3 (155.52 Mbit/s) in-
terface device. The chip performs all necessary
serial-to-parallel and parallel-to-serial functions in
conformance with SONET/SDH transmission stan-
dards. The device is suitable for SONET-based ATM
applications. Figure 1 shows a typical network appli-
cation.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3035
transceiver chip allowing the use of a slower external
transmit clock reference. Clock recovery is performed
on the device by synchronizing its on-chip VCO directly
to the incoming data stream. The S3035 also per-
forms SONET/SDH frame detection. The chip can be
used with a 19.44, 38.88, 51.84 or 77.76 MHz refer-
ence clock, in support of existing system clocking
schemes. Redundant transmit and receive serial I/O
can be used to implement redundant physical layers
in ATM backbones.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3035 is pack-
aged in a 14 mm 80 PQFP, offering designers a
small package outline.
ORX
ORX
OTX
OTX
SONET/SDH
Transceiver
S3035
8
8
Processor
Interface
Network
S3035
S3035
S3035
®
1

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S3033 Summary of contents

Page 1

DEVICE SPECIFICATION SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR BiCMOS LVPECL CLOCK GENERATOR SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER FEATURES • Complies with Bellcore and ITU-T specifications • On-chip high-frequency PLLs for clock generation and clock recovery • Supports 155.52 ...

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S3035 SONET OVERVIEW Synchronous Optical Network (SONET stan- dard for connecting one fiber system to another at the optical level. SONET, together with the Synchro- nous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard ...

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SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR S3035 OVERVIEW The S3035 transceiver implements SONET/SDH se- rialization/deserialization, transmission, and frame detection/recovery functions. The block diagram in Figure 4 shows the basic operation of the chip. This chip can be used to implement the front ...

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S3035 Figure 4. S3035 Transceiver Functional Block Diagram Transmitter PIN[7:0] PICLK LLEB SLPTIME RSTB TSTRST MODE 0 MODE 1 REFCLKP/N TTLREF Receiver SDTTL SDPECL OOF DLEB RSD0P RSD1P/N X RSDSEL TESTEN 4 SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR 8 8:1 ...

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SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR S3035 TRANSCEIVER FUNCTIONAL DESCRIPTION TRANSMITTER OPERATION The S3035 transceiver chip performs the serializing stage in the processing of a transmit SONET STS-3 or STS-12 bit serial data stream. It converts the 8-bit parallel 19.44 or 77.76 ...

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S3035 RECEIVER OPERATION The S3035 transceiver chip provides the first stage of digital processing of a receive SONET STS-3 or STS-12 bit-serial stream. It converts the bit-serial 155.52 or 622.08 Mbit/sec data stream into a 19.44 or 77.76 Mbps 8-bit ...

Page 7

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Backup Reference Generator The backup reference generator seen in Figure 4 provides backup reference clock signals to the clock recovery block when the clock recovery block de- tects a loss of signal or out of lock ...

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S3035 OTHER OPERATING MODES Diagnostic Loopback When the Diagnostic Loopback Enable (DLEB) input is active, a loopback from the transmitter to the re- ceiver at the serial data rate can be set up for diagnostic purposes. SDPECL must be High ...

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SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Table 4. S3035 Transmitter Pin Assignment and Descriptions ...

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S3035 Table 5. S3035 Receiver Pin Assignment and Descriptions ...

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SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Table 5. S3035 Receiver Pin Assignment and Descriptions (Continued ...

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S3035 Table 6. S3035 Common Pin Assignment and Descriptions ...

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SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Table 6. S3035 Common Pin Assignment and Descriptions (Continued ...

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S3035 Figure 6. 80 PQFP Package Thermal Management Device S3035 14 SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR ja Still Air Max Still Air 85˚C 35˚C/W Dimensions are in mm. April 12, 2000 / Revision D ...

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SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Figure 7. S3035 Pinout Assignments 38MHZCLK 1 CLKVCC 2 51MHZCLK 3 TXCOREGND 4 5 TXCOREVCC TTLREF 6 7 REFCLKN REFCLKP 8 AVCC1 9 AGND1 10 CAP2 11 CAP1 12 13 AGND0 14 AVCC0 15 TSTRST LLEB ...

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S3035 Table 7. Performance Specifications ...

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SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Table 8. Absolute Maximum Ratings ...

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S3035 Table 11. LVPECL Input/Output DC Characteristics Parameter Symbol V IL Input Low Voltage V IH Input High Voltage V IL Input Low Voltage V IH Input High Voltage V ID Input Diff. Voltage I IHD Diff. Input High Current ...

Page 19

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Figure 8. Transmitter Input Timing PCLK PICLK PIN[7:0] 1. When a setup time is specified on LVTTL signals between an input and a clock, the setup time is the time in nanoseconds from the 50% cross ...

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S3035 RECEIVER FRAMING Figure 10 shows a typical reframe sequence in which a byte realignment is made. The frame and byte boundary detection is enabled by the rising edge of OOF and remains enabled while OOF is High. Both boundaries ...

Page 21

APPLICATION NOTE SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR S3035 WITH DATA CLOCK SYNCHRONOUS TO REFERENCE CLOCK In some applications it is necessary to "forward clock" the data in a SONET/SDH system. In this ap- plication the reference clock from which the High ...

Page 22

S3035 Ordering Information Applied Micro Circuits Corporation • 6290 Sequence Dr.,5 San Diego, CA 92121 ...

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