S3033 AMCC (Applied Micro Circuits Corp), S3033 Datasheet - Page 6

• Manufacturer Part Number: S3033
• Description: Bicmos Lvpecl Clock Generator Sonet/sdh/atm Oc-12 Transmitter And Sonet/sdh/atm Oc-3/oc-12 Transceiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

RECEIVER OPERATION
The S3035 transceiver chip provides the first stage
of digital processing of a receive SONET STS-3 or
STS-12 bit-serial stream. It converts the bit-serial
155.52 or 622.08 Mbit/sec data stream into a 19.44
or 77.76 Mbps 8-bit parallel data format.
Clock recovery is performed on the selected incom-
ing serial scrambled NRZ data stream. A 19.44 or
77.76 MHz reference clock is required for phase
locked loop start-up and proper operation under loss
of signal conditions. An integral prescaler and phase
locked loop circuit is used to multiply this reference
to the nominal bit rate.
A loopback mode is provided for diagnostic loopback
(transmitter to receiver).
Clock Recovery
Clock recovery, as shown in the block diagram in
Figure 4, generates a clock that is at the same fre-
quency as the incoming data bit rate at the RSD
input or, in loopback, the transmitter data output. The
clock is phase aligned by a PLL so that it samples
the data in the center of the data eye pattern.
The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency discriminator. Out-
put pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of the
Voltage Controlled Oscillator (VCO), which gener-
ates the recovered clock.
Figure 5. Clock Recovery Jitter Tolerance
6
Jitter
Amplitude
(Ul p-p)
S3035
0.15
1.5
15
Minimum proposed
tolerance
(TA-NWT-000253)
30
300
Jitter Frequency (Hz)
6.5k
25k 65k
OC-3
OC-12
250k
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the frequency
of the incoming signal varies by greater than the
value specified in Table 7 with respect to REFCLKP/
N, the PLL will be declared out of lock, and the PLL
will lock to the reference clock. The assertion of LOS
will also cause an out of lock condition.
The loop filter transfer function is optimized to en-
able the PLL to track the jitter, yet tolerate the
minimum transition density expected in a received
SONET data signal. This transfer function yields the
typical capture time stated in Table 7 for random
incoming NRZ data.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 5.
Lock Detect
The S3035 contains a lock detect circuit which moni-
tors the integrity of the serial data inputs. If the
received serial data fails the run length or frequency
test, the PLL will be forced to lock to the local refer-
ence clock. This will maintain the correct frequency
of the POCLK output under loss of signal or loss of
lock conditions. If the serial data inputs have a run
length of 80-bit times with no transitions, the PLL will
be declared out of lock. In addition, if the recovered
clock frequency deviates from the local reference
clock frequency by more than the specified ppm, the
PLL will also be declared out of lock. The lock detect
circuit will poll the input data stream in an attempt to
reacquire lock to data. If the recovered clock fre-
quency is determined to be within the specified ppm
and the run length check indicates valid data, the
PLL will be declared in lock and the lock detect out-
put will go active. See Table 7.
April 12, 2000 / Revision D