S3033 AMCC (Applied Micro Circuits Corp), S3033 Datasheet - Page 8

• Manufacturer Part Number: S3033
• Description: Bicmos Lvpecl Clock Generator Sonet/sdh/atm Oc-12 Transmitter And Sonet/sdh/atm Oc-3/oc-12 Transceiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is active, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for
diagnostic purposes. SDPECL must be High for di-
agnostic loopback.
The differential serial output data from the transmitter
is routed to the clock recovery unit and serial-to-par-
allel block in place of the normal Receive Data
Stream (RSD).
Line Loopback
When Line Loopback Enable (LLEB) is active, a
loopback from the receiver to the transmitter at the
serial data rate can be set up for facility loopback
testing. The recovered clock is used to retime the
incoming data before driving the TSDP/N outputs. In
line loopback mode, the TSCLKP/N outputs will be
driven by the receiver recovered clock.
Serial Loop Timing
In Serial Loop Timing mode (SLPTIME), the clock
synthesizer PLL of the S3035 is bypassed, and the
timing of the entire transmitter section is controlled
by the recovered receive serial clock. This mode is
entered by using the SLPTIME input.
8
S3035
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
In this mode the REFCLKP/N input is not used, and
the MODE[1:0] inputs are ignored for all transmit
functions. It should be carefully noted that the inter-
nal PLL continues to operate in this mode, and
continues as the source for the 38.51 MHZCLK, and
if this signal is being used, the REFCLKP/N and
MODE[1:0] inputs must be properly driven.
Forward Clocking
For both 77.78 MHz and 38.88 MHz reference op-
eration, the S3035 operates in the forward clocking
mode. The PLL locks the PCLK output of the trans-
mitter section to the REFCLK with a fixed and
repeatable phase relation. This allows the transmit-
ter data source to also be the timing source for the
serial clock synthesis.
The rising edge of PCLK is locked to the rising edge
of REFCLKP, with a maximum delay of 8 to 10 nsec
due to the PCLK TTL output driver.
For operation at 19.44 MHz and 51.84 MHz refer-
ences, separate timing paths are used for PLL
control and PCLK generation, and forward clocking
is not recommended.
Looptime Mode
When Serial Looptime Enable (SLPTIME) is active,
the serial recovered clock from the receiver will re-
place the serial clock in the transmitter section.
April 12, 2000 / Revision D