S3033 AMCC (Applied Micro Circuits Corp), S3033 Datasheet - Page 7

• Manufacturer Part Number: S3033
• Description: Bicmos Lvpecl Clock Generator Sonet/sdh/atm Oc-12 Transmitter And Sonet/sdh/atm Oc-3/oc-12 Transceiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

April 12, 2000 / Revision D
Backup Reference Generator
The backup reference generator seen in Figure 4
provides backup reference clock signals to the clock
recovery block when the clock recovery block de-
tects a loss of signal or out of lock condition. It
contains a counter that divides the clock output from
the clock recovery block down to the same fre-
quency as the reference clock, REFCLKP/N.
Frame and Byte Boundary Detection
The frame and byte boundary detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by three consecutive A2
bytes. Framing pattern detection is enabled and dis-
abled by the out-of-frame (OOF) input. Detection is
enabled by a rising edge on OOF, and remains en-
abled for the duration that OOF is set High. It is
disabled when a framing pattern is detected and
OOF is no longer set High. When framing pattern
detection is enabled, the framing pattern is used to
locate byte and frame boundaries in the incoming
data stream (RSD or looped transmitter data). The
timing generator block takes the located byte bound-
ary and uses it to block the incoming data stream
into bytes for output on the parallel output data bus
(POUTP/N[7:0]). The frame boundary is reported on
the Frame Pulse (FP) output when any 48-bit pattern
matching the framing pattern is detected on the in-
coming data stream. When framing pattern detection
is disabled, the byte boundary is frozen to the loca-
tion found when detection was previously enabled.
Only framing patterns aligned to the fixed byte
boundary are indicated on the FP output.
The probability that random data in an STS-3 or STS-
12 stream will generate the 48-bit framing pattern is
extremely small. It is highly improbable that a mimic
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
pattern would occur within one frame of data. There-
fore, the time to match the first frame pattern and to
verify it with down stream circuitry, at the next occurrence
of the pattern, is expected to be less than the required
250 s, even for extremely high bit error rates.
Once down stream overhead circuitry has verified
that frame and byte synchronization are correct, the
OOF input can be set Low to disable the frame
search process from trying to synchronize to a
mimic frame pattern
Serial-to-Parallel Converter
The serial-to-parallel converter consists of three
8-bit registers. The first is a serial-in, parallel-out
shift register, which performs serial-to-parallel con-
version clocked by the clock recovery block. The
second is an 8-bit internal holding register, which
transfers data from the serial-to-parallel register on
byte boundaries as determined by the frame and
byte boundary detection block. On the falling edge
of the free running POCLK, the data in the holding
register is transferred to an output holding register
which drives POUT[7:0].
The delay through the serial-to-parallel converter
can vary from 1.5 to 3.5 byte periods (12 to 28 serial
bit periods) measured from the first bit of an incom-
ing byte to the beginning of the parallel output of
that byte. The variation in the delay is dependent on
the alignment of the internal parallel load timing,
which is synchronized to the data byte boundaries,
with respect to the falling edge of POCLK, which is
independent of the byte boundaries. The advantage of
this serial-to-parallel converter is that POCLK is nei-
ther truncated nor extended during reframe
sequences. (See Figure 10.)
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