XR17D154 Exar Corporation, XR17D154 Datasheet - Page 10

no-image

XR17D154

Manufacturer Part Number
XR17D154
Description
Four-channel Pci-bus Uart
Manufacturer
Exar Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR17D154CV
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR17D154CV
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
Part Number:
XR17D154CV-F
Manufacturer:
Exar
Quantity:
365
Part Number:
XR17D154CV-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR17D154IV
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR17D154IV-F
Manufacturer:
ADI
Quantity:
1 046
Part Number:
XR17D154IV-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Company:
Part Number:
XR17D154IV-F
Quantity:
15
áç
áç
áç
áç
PRELIMINARY
A
0x18h
DDRESS
0x0C
0x1C
0x2C
0x00
0x04
0x08
0x10
0x14
0x20
0x24
0x28
31:16
15:0
31:28
27
26:25
24
23
22:16
15:9,7,
5,4,3,2
8
6
1
0
31:8
7:0
31:24
23:16
15:8
7:0
31:11
10:0
31:0
31:0
31:0
31:0
31:0
31:0
31:16
B
ITS
R-Reset
RWR
RWR
RWR
RWR
T
WO
WO
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
T
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
YPE
ABLE
1
1
1
1: PCI L
Device ID (Exar device ID number or from EEPROM)
Vendor ID (Exar ID or from EEPROM) specified by PCISIG
Status bits (error reporting bits)
Target Abort. Set whenever D154 terminates with a target abort.
DEVSEL# timing.
Unimplemented bus master error reporting bit
Fast back to back transactions are supported
Reserved Status bits
Command bits (reserved)
SERR# driver enable. Logic 1=enable driver and 0=disable driver
Parity error enable. Logic 1=respond to parity error and 0=ignore
Command controls a device’s response to mem space accesses:
0=disable mem space accesses, 1=enable mem space accesses
Command controls a device’s response to I/O space accesses:
0 = disable I/O space accesses 1 = enable I/O space accesses
Class Code (Simple 550 Communication Controller).
Revision ID (Exar device revision number)
BIST (Built-in Self Test)
Header Type (a single function device with one BAR)
Unimplemented Latency Timer (needed only for bus master)
Unimplemented Cache Line Size
Memory Base Address Register (BAR)
Claims a 2K address space for the memory mapped UARTs
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
Reserved
Subsystem ID (write from external EEPROM by customer)
OCAL
B
US
C
ONFIGURATION
10
D
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
ESCRIPTION
S
PACE
R
EGISTERS
R
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
ESET
0x070002
000 0000
0x13A8
0xX000
0x0154
0x0000
0x0000
XR17D154
(
0000
0x00
0x01
0x00
0x00
0x00
0x00
REV. P1.0.0
HEX
00
0
0
1
0
0
0
0
V
ALUE
)

Related parts for XR17D154