XR17D154 Exar Corporation, XR17D154 Datasheet - Page 17

• Manufacturer Part Number: XR17D154
• Description: Four-channel Pci-bus Uart
• Manufacturer: Exar Corporation

XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
REV. P1.0.0
TIMER [15:8] - (default 0x00)
Reserved.
TIMERMSB [31:24] and TIMERLSB [23:16]
TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit [0] of the
TIMERLSB with most-significant-bit being bit [7] in TIMERMSB. Notice that these registers do not hold the
current counter value when read. Reading the TIMERCNTL register will clear its interrupt. Default value is zero
(timer disabled) upon powerup and reset.
Each bit selects 8X or 16X sampling rate for that UART channel, bit-0 is channel 0. Logic 0 (default) selects
normal 16X sampling with logic one selects 8X sampling rate. Transmit and receive data rates will double by
selecting 8X.
Reserved.
The 8-bit Reset register [RESET] provides the software with the ability to reset the UART(s) when there is a
need. Each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. All registers in that
channel will be reset to the default condition, see
3=1 resets channel 3..
2.2.3
2.2.4
2.2.5
B it-1 5 B it-1 4 B it-1 3 B it-1 2 B it-1 1 B it-1 0
8XMODE [7:0] - (default 0x00)
REGA [15:8] -
RESET [23:16] - (default 0x00)
TIM E RM S B R eg ister
(default 0x00)
B it-7 B it-6
R s vd
B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
R svd
R svd
B it-7 B it-6 B it-5 B it-4 B it-3 Bit-2 Bit-1 Bit-0
Individual UA R T Channel 8X C lock M ode E nable
1 6 -B it T im e r/C o u n te r P ro g ra m m a b le R e g iste rs
R s vd
Individual U A RT C hannel R eset E nable
R svd
R svd
B it-5
R s vd
B it-9 B it-8
T IM E R C N T L R eg ister
R svd R svd C h-3 C h-2 C h-1 C h-0
R svd R svd C h-3 C h-2 C h-1 C h-0
8XM O D E R egister
RES ET Register
M P IO [0 ]
C o n tro l
B it-4
Table 18
17
S e le c t
C lo c k
B it-3
B it-7
for details. Bit-0 =1 resets UART channel 0 with bit-
R e -trig g e r
B it-2
S in g le /
B it-6
B it-1
S ta rt/
S to p
B it-5
TIM E RL SB R eg ister
B it-0
E n a b le
IN T
B it-4
B it-3
PRELIMINARY
B it-2
áç
áç
áç
áç
B it-1 B it-0