XR17D154 Exar Corporation, XR17D154 Datasheet - Page 31

• Manufacturer Part Number: XR17D154
• Description: Four-channel Pci-bus Uart
• Manufacturer: Exar Corporation

XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
REV. P1.0.0
N
The transmitter section comprises of a 64 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an
8-bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte
from the FIFO when the FIFO is enabled by FCR bit-0. TSR shifts out every data bit with the 16X or 8X internal
clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of data bits,
inserts the proper parity bit if enable, and adds the stop bit(s). The status of the THR and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is also the
input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. A THR empty
interrupt can be generated when it is enabled in IER bit-1.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
F
5.6
T
5.6.1
5.6.2
A
OTE
IGURE
1 1 0 0
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
ABLE
A3-A0
DDRESS
: MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR17D154. They are present for 16C550
compatibility during Internal loopback, see
11: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
14. T
Transmitter
(8 X M O D E
1 6 X o r 8 X
Transmit Holding Register (THR)
Transmitter Operation in non-FIFO
XCHAR
R e g is te r)
XOFF1
XOFF2
XON1
XON2
N
R
C lo c k
AME
RANSMITTER
EG
D a ta
B y te
W
R
EAD
RITE
W
W
W
W
R
/
O
PERATION IN NON
B
T ra n s m it S h ift R e g is te r (T S R )
Bit-7
Bit-7
Bit-7
Bit-7
IT
0
-7
B
Bit-6
Bit-6
Bit-6
Bit-6
T ra n s m it
IT
R e g is te r
0
H o ld in g
-6
(T H R )
-FIFO M
Figure 13
B
Bit-5
Bit-5
Bit-5
Bit-5
IT
0
-5
ODE
31
.
B
Bit-4
Bit-4
Bit-4
Bit-4
IT
0
-4
T H R In te rru p t (IS R b it-1 )
E n a b le d b y IE R b it-1
B
Bit-3
Bit-3
Bit-3
Bit-3
IT
0
-3
M
S
B
B
Bit-2
Bit-2
Bit-2
Bit-2
IT
0
-2
S
HADED BITS ARE ENABLED BY
Xon Det.
Indicator
B
Bit-1
Bit-1
Bit-1
Bit-1
IT
PRELIMINARY
-1
T X N O F IF O 1
L
S
B
áç
áç
áç
áç
Xoff Det.
Indicator
B
Bit-0
Bit-0
Bit-0
Bit-0
IT
-0
EFR B
C
after read
Self-clear
OMMENT
IT
-4.